GPIO number in iMX8

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GPIO number in iMX8

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mrigendra_chaub
Contributor III

Hi,

I am confused about gpio number calculation, in uboot there is commit on this file

arch/arm/include/asm/arch-imx8/gpio.h

commit 3733fc85c1f29f2d0ac2af42eca64d5939902fe3
Author: Adrian Alonso <adrian.alonso@nxp.com>
Date: Tue Mar 8 14:53:31 2016 -0600

MLK-14938-21 mxc_gpio: add support for i.MX8

Add support for iMX8 SoC platforms, and extend to support LSIO GPIO0..GPIO7 ports.
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX platforms,
so we have to adjust the index accordingly.

where, to calculate gpio number we use this formula,

+/* IMX8 the GPIO index is from 0 not 1 */
+#define IMX_GPIO_NR(port, index) (((port)*32)+((index)&31))
+
+#endif /* __ASM_ARCH_IMX8_GPIO_H */

But in kernel to get gpio number we are using this formula and it works

#define IMX_GPIO_NR(bank, pin) (480 - (bank * 32) + (pin & 0x1f))

To get gpio3_25 both gives different gpio number. 

Which one is correct? Kindly clarify.

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Maddis
Contributor IV

Is it really so that there isn't macro in kernel similar to u-boot that'll return the GPIO - number? I really don't care how the numbering goes if you can get it with that macro and it would also made it independent from processor to processor.

Here is the formula I've used to calculate GPIO number atm: (9 - gpio_bank) * 32 + 192 + gpio_bit 

Far cry from imx6's 'gpio_bank * 32 + gpio_bit' but oh well.

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felixradensky
Contributor IV

Hi,

We have different GPIO numbering in u-boot and kernel because u-boot defines aliases for GPIO controllers in DTS but kernel does not. See

fsl-imx8qm.dtsi\dts\arm\arch - uboot-imx - i.MX U-Boot 

fsl-imx8qm.dtsi\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

The GPIO numbering in i.MX8QM kernel is really backwards. I think it's a bug that should be fixed.

i.MX8M and i.MX8M Mini kernels have correct numbering, but i.MX8QM and i.MX8QXP have not.

Felix.

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art
NXP Employee
NXP Employee

The i.MX8QuadMax Reference Manual document indicates that the processor contains 7 GPIO ports, GPIO0 to GPIO6. Each of GPIO0 to GPIO5 ports contains 32 signals, the GPIO6 port contains 22 signals, totally 32*6 + 22 = 214 signals.

Have a great day,

Artur

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mrigendra_chaub
Contributor III

Does that mean formula should always be this, 

#define IMX_GPIO_NR(port, index) (((port)*32)+((index)&31)) ?

and this formula is wrong?

#define IMX_GPIO_NR(bank, pin) (480 - (bank * 32) + (pin & 0x1f))

I think both are wrong.

But then how in kernel /sys/class/gpio we get these chip numbers (in bold)

lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpio448 -> ../../devices/platform/5d090000.gpio/gpiochip1/gpio/gpio448
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip208 -> ../../devices/platform/5a810000.i2c/i2c-4/i2c-8/8-001d/gpio/gpiochip208
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip216 -> ../../devices/platform/5a810000.i2c/i2c-4/i2c-8/8-001a/gpio/gpiochip216
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip224 -> ../../devices/platform/58222000.gpio/gpio/gpiochip224
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip256 -> ../../devices/platform/5d0f0000.gpio/gpio/gpiochip256
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip288 -> ../../devices/platform/5d0e0000.gpio/gpio/gpiochip288
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip320 -> ../../devices/platform/5d0d0000.gpio/gpio/gpiochip320
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip352 -> ../../devices/platform/5d0c0000.gpio/gpio/gpiochip352
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip384 -> ../../devices/platform/5d0b0000.gpio/gpio/gpiochip384
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip416 -> ../../devices/platform/5d0a0000.gpio/gpio/gpiochip416
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip448 -> ../../devices/platform/5d090000.gpio/gpio/gpiochip448
lrwxrwxrwx 1 root root 0 2019-05-29 10:04 gpiochip480 -> ../../devices/platform/5d080000.gpio/gpio/gpiochip480

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art
NXP Employee
NXP Employee

Actually, I even don't know what this IMX_GPIO_NR parameter refers to. As I told before, from the hardware point of view, the i.MX8QuadMax processor has 214 Low Speed I/O (LSIO) signals, divided to 6 banks by 32 signals and 1 bank by 22
signals and available as the ALT3 IOMUX function on some of the processor's pads. For details, you can download the latest version of the i.MX Pins Tool software:

https://www.nxp.com/pages/pins-tool-for-i.mx-application-processors:PINS-TOOL-IMX

https://www.nxp.com/pages/pins-tool-for-i.mx-application-processors:PINS-TOOL-IMX?tab=Design_Tools_T...

select the i.MX8QuadMax processor there and then check the exact LSIO signals location on the external pads.

Best Regards,
Artur

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