Flexcan mb queue

[Markheadson]

Hello

I's possible on iMX8 M4 side, FreeRtos to organize Flexcan MB with different index but same id at 0x0 (accept all) in order to simulate a long fifo (like its done with Linux Flexcan driver if Ive well understood)

When a MB is full, the next free one will be used.

Thanks

[Markheadson]

Sorry, I mean RX mailbox.with linux driver 62 mailboxes are organized in order to simulate a fifo:

from driver docs:The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames, while the mailbox mode uses a software FIFO with a depth of up to 62 CAN frames. With the help of the bigger buffer, the mailbox mode performs better under high system load situations.

https://docs.kernel.org/networking/device_drivers/can/freescale/flexcan.html

I just done it on M4 by modifying original Flexcan driver

THKS

[kef2]

What do you actually mean regarding Linux. AFAIK Linux flexcan driver doesn't support in order TX FIFO. Messages are sent according to their ID priority. Hm, same ID? Having enough spare TX MB's, they perhaps could be send in order, but once no spare MB's, I fear your "FIFO" would break even with same ID. 

Implementing FIFO is possible with MB index based TX priority. You fill MB0, enable interrupt only for MB0. Next TX message is written to MB1, disabling MB0 interrupt and enabling MB1 interrupt and so on until you have spare MB's. When TX interrupt happens you reset TX MB index. Something like that.

[Bio_TICFSL]

Hello,

That's  not possible with MX8 M4 core.

Regards

[Markheadson]

Sorry, I mean RX mailbox.with linux driver 62 mailboxes are organized in order to simulate a fifo:

from driver docs:The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames, while the mailbox mode uses a software FIFO with a depth of up to 62 CAN frames. With the help of the bigger buffer, the mailbox mode performs better under high system load situations.

https://docs.kernel.org/networking/device_drivers/can/freescale/flexcan.html

I just done it on M4 by modifying original Flexcan driver

THKS

[kef2]

No matter what Linux driver docs say, filling spare empty FlexCAN buffers with ID+data breaks FIFO order. Messages are send according to transmit buffer priority, which can be either a) low order buffer first or b) message ID based priority. Say at some time you have 10 empty MB's. With TX priority set to lowest MB first, you can schedule those 10 MB's to send messages in FIFO order. But once you have no spare buffer, driver would chose least free MB again, which would break FIFO order. The same break of FIFO happens in case your first MB(s) from your burst of messages is send before you complete preparing the rest of MBs burst for transmission.