FlexSPI with AHB prefetch causes hard fault

[stmatscaps]

Hi,

we have a custom board with an i MX.8 M Nano chip that communicates via FlexSPI with an FPGA with AHB reads and writes from the CM7 core. This is working fine in general.

Now we are looking into improving the performance by enabling prefetch for AHB reads.

The relevant FlexSPI configuration looks like this:

    flexspi_config_t config;
    FLEXSPI_GetDefaultConfig(&config);

    config.enableSckFreeRunning = true;
    config.ahbConfig.enableAHBPrefetch    = true;
    config.ahbConfig.enableAHBBufferable  = false;
    config.ahbConfig.enableReadAddressOpt = false;
    config.ahbConfig.enableAHBCachable    = false;
    config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
    config.enableCombination = true;

    FLEXSPI_Init(FLEXSPI, &config);

With "config.ahbConfig.enableAHBPrefetch = true;" we are getting the hard fault on the first AHB read attempt, while with "config.ahbConfig.enableAHBPrefetch = false;" everything is working as expected. I can see with a logic analyzer that with "config.ahbConfig.enableAHBPrefetch = true;" there is no activity at all on the SPI bus when the AHB read is triggered, the hard fault occurs immediately.

What can be the reason for the hard fault if only AHB prefetch is enabled with no other changes compared to the working configuration? Are we missing further settings that need to be changed from the default to make AHB prefetch work?

In that context we also want to configure the prefetch size. Section "10.2.4.10.3 AHB RX Buffer Management" of the i.MX 8M Nano Applications Processor Reference Manual describes how to configure the prefetch sizes for different master IDs.

Where are the "master IDs" documented, and what is the master ID for the CM7 core in this context? I was not able not find this information in the Reference Manual.

Thank you
Stephan

[Zhiming_Liu]

Hi @stmatscaps 

Configuring the AHB RX Buffer is necessary, but the RM hides the CM7 master ID. I need some time to confirm the exact value. In the meantime, you can try master id=6.

Best Regards,
Zhiming

[stmatscaps]

Hi @Zhiming_Liu ,

do you have an update regarding the master IDs in the meantime?

Thank you
Stephan

[Zhiming_Liu]

Hi @stmatscaps 

This is still being verified; we need the R&D team to provide the information.

Best Regards,
Zhiming

[stmatscaps]

you can try master id=6

I tried master ID 6, and the hard fault still occurs.

I'm configuring an 8-byte buffer in slot 0 for master ID 6. At the SDK level:

    flexspi_config_t config;
    FLEXSPI_GetDefaultConfig(&config);
    config.ahbConfig.enableAHBPrefetch    = true;
    config.ahbConfig.buffer[0].masterIndex = 6;
    config.ahbConfig.buffer[0].bufferSize = 8;

 This results in the following AHBRXBUF register contents:

AHBRXBUF0CR0 0x80060001
AHBRXBUF1CR0 0x800f0000
AHBRXBUF2CR0 0x800f0000
AHBRXBUF3CR0 0x800f0000
AHBRXBUF4CR0 0x800f0000
AHBRXBUF5CR0 0x800f0000
AHBRXBUF6CR0 0x80000020
AHBRXBUF7CR0 0x80000020

[stmatscaps]

Hi  ,

but the RM hides the CM7 master ID

Do I understand it correctly that "RM" means Reference Manual?

And when you confirm the master ID, could you please document all master IDs for future reference here?

I see that the function FLEXSPI_GetDefaultConfig() in the MCUXPresso SDK configures a 256 byte RX buffer in AHBRXBUF6CR0 for master ID 0:

https://github.com/nxp-mcuxpresso/mcuxsdk-core/blob/4cc1d817b8142fed4fd6cfcbcf0a393a954a425b/drivers...

    FLEXSPI_Memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
    /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */
    for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++)
    {
        config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
        config->ahbConfig.buffer[i].masterIndex = 0xFU; /* Invalid master index which is not used, so will never hit. */
        config->ahbConfig.buffer[i].bufferSize =
            0; /* Default buffer size 0 for buffer0 to buffer(FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 3U)*/
    }

    for (uint8_t i = ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U);
         i < (uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
    {
        config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */
        config->ahbConfig.buffer[i].bufferSize     = 256U; /* Default buffer size 256 bytes. */
    }

Thank you
Stephan