Take a look at imx8ulp_clk_cgc1_init in drivers/clk/imx/clk-imx8ulp.c, specifically lines 219 through 221, see here.
clks[IMX8ULP_CLK_AUD_CLK1] = imx_clk_hw_mux2("aud_clk1", base + 0x900, 0, 3, aud_clk1_sels, ARRAY_SIZE(aud_clk1_sels));
clks[IMX8ULP_CLK_SAI4_SEL] = imx_clk_hw_mux2("sai4_sel", base + 0x904, 0, 2, sai45_sels, ARRAY_SIZE(sai45_sels));
clks[IMX8ULP_CLK_SAI5_SEL] = imx_clk_hw_mux2("sai5_sel", base + 0x904, 8, 2, sai45_sels, ARRAY_SIZE(sai45_sels));
Now, look at the i.MX 8ULP Processor Reference Manual, IMX8ULPRM (here), section 7.6.1.1 AD_CGC memory map. You'll see in the table there are two additional registers at 0x908 and 0x90C that are not included in the driver.
The consequence of not including these registers is that TPM6 and TPM7 (and also, I suppose MQS1) cannot be configured to use a PCC4 clock via the device tree.
I had added tpm6 and tpm7 nodes to imx8ulp.dtsi and configured them to use the clocks <&pcc4 IMX8ULP_CLK_TPM6> and <&pcc4 IMX8ULP_CLK_TPM7>:
per_bridge4: bus@29800000 {
tpm6: pwm@29820000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x29820000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_TPM6>;
assigned-clocks = <&pcc4 IMX8ULP_CLK_TPM6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
#pwm-cells = <3>;
status = "disabled";
};
tpm7: pwm@29830000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x29830000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_TPM7>;
assigned-clocks = <&pcc4 IMX8ULP_CLK_TPM7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
#pwm-cells = <3>;
status = "disabled";
};
};
However, because the default value of TPM6_7CLK (CGC1 register 0x908) is 0x00000000, TPM6CLK and TPM7CLK are both configured to use AUD_PLL_CLK1, an audio clock generated from the Audio PLL (PLL3PFD1DIV1), not the PCC4 clocks I selected via the device tree.
I resolved this by adding a call to writel to explicitly set register 0x908.
static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
{
...
/* There is a register called TPM6_7CLK at offset 0x908 that is not set by
this driver. By default, it is equal to 0x00000000, which causes TPM6
and TPM7 to use as their clock source an "Audio clock generated from the
Audio PLL in AD - PLL3PFD1DIV1", rather than the main reference clock.
By setting this register to 0x00000303, the main reference clock is used
for both TPM6 and TPM7. See IMX8ULPRM, the "i.MX 8ULP Processor
Reference Manual", section "Clock Generation and Control (CGC1)" for
more information on this register. */
writel(0x00000303, base + 0x908);
imx_check_clk_hws(clks, clk_data->num);
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
}
While this solves my problem for now, it would be nice if there were a way to set this clock configuration properly via the device tree, but that would require the clk-imx8ulp.c clock driver to configure this register.
Thanks for your time looking into this!
