Fail to load vivante GPU driver

[williamtung]

Hi,

We encountered a strange issue to load vivate GPU driver during power up. Here is the scenario:

1. Build the vivate GPU driver into kernel

2. Power on the solo board and the kernel stuck at infinite loop in _ResetGPU.

3. Hard reset the board and the board can pass the _ResetGPU function to complete booting

4. Hard reset at anytime before the GPU driver loading doesn't clear this failure. Ex, hard reset in Uboot or any driver/function before vivate GPU driver can't clear the failure.

5. The problem comes back when cut power to power cycle the board.

It sounds weird but it only happens to solo board not quad board. (we have both version on same layout) Does anyone see this issue before?

Thanks.

[mtx512]

We have same issue with the LDO patch it continually reports the "“COULD NOT SET GP VOLTAGE!!!!”  message. Looks the voltage cannot be set on the anatop regulator.

Is there a freescale fix for this?

[Martin1z]

Same problem here. The suggested delay workaround does resolv this situation.

[williamtung]

Hi Prabhu,

I've tried rel_imx_3.0.35_1.1.0 and imx-android-13.4.1. Both have the same GPU boot issue.

I found two methods to get through the GPU boot issue.

1. Apply LDO patch as Freescale provided.

-- This introduces new side effect which kernel keeps popping “COULD NOT SET GP VOLTAGE!!!!” error message.

-- I’d like to spend more time on this because internal LDO is a known issue and we need to apply the patch anyways.

-- I use the workaround below for one of our customer because I didn’t see wandboard.org apply the LDO patch on their solo board.

2. Workaround adding delay:

arch/arm/mach-mx6/mx6_anatop_regulator.c

static int pu_enable(struct anatop_regulator *sreg)

{

unsigned int reg, vddsoc;

int ret = 0;

/*get PU related clk to finish PU regulator power up*/

if (!get_clk) {

if (!cpu_is_mx6sl()) {

gpu3d_clk = clk_get(NULL, "gpu3d_clk");

if (IS_ERR(gpu3d_clk))

printk(KERN_ERR "%s: failed to get gpu3d_clk!\n"

, __func__);

gpu3d_shade_clk = clk_get(NULL, "gpu3d_shader_clk");

if (IS_ERR(gpu3d_shade_clk))

printk(KERN_ERR "%s: failed to get shade_clk!\n"

, __func__);

if (IS_ERR(vpu_clk))

printk(KERN_ERR "%s: failed to get vpu_clk!\n",

__func__);

}

gpu2d_clk = clk_get(NULL, "gpu2d_clk");

if (IS_ERR(gpu2d_clk))

printk(KERN_ERR "%s: failed to get gpu2d_clk!\n",

__func__);

gpu2d_axi_clk = clk_get(NULL, "gpu2d_axi_clk");

if (IS_ERR(gpu2d_axi_clk))

printk(KERN_ERR "%s: failed to get gpu2d_axi_clk!\n",

__func__);

openvg_axi_clk = clk_get(NULL, "openvg_axi_clk");

if (IS_ERR(openvg_axi_clk))

printk(KERN_ERR "%s: failed to get openvg_axi_clk!\n",

__func__);

get_clk = 1;

}

if (external_pureg) {

/*enable extern PU regulator*/

ret = regulator_enable(pu_regulator);

if (ret < 0)

printk(KERN_ERR "%s: enable pu error!\n", __func__);

} else {

/*Track the voltage of VDDPU with VDDSOC if use internal PU

*regulator.

*/

reg = __raw_readl(ANADIG_REG_CORE);

vddsoc  = reg & (ANADIG_REG_TARGET_MASK <<

ANADIG_REG2_SOC_TARGET_OFFSET);

reg &= ~(ANADIG_REG_TARGET_MASK <<

ANADIG_REG1_PU_TARGET_OFFSET);

reg |= vddsoc >> (ANADIG_REG2_SOC_TARGET_OFFSET

-ANADIG_REG1_PU_TARGET_OFFSET);

__raw_writel(reg, ANADIG_REG_CORE);

}

/* Need to wait for the regulator to come back up */

/*

* Delay time is based on the number of 24MHz clock cycles

* programmed in the ANA_MISC2_BASE_ADDR for each

* 25mV step.

*/

udelay(150);

/*enable gpu clock to powerup GPU right.*/

if (get_clk) {

if (!cpu_is_mx6sl()) {

clk_enable(gpu3d_clk);

clk_enable(gpu3d_shade_clk);

clk_enable(vpu_clk);

}

clk_enable(gpu2d_clk);

clk_enable(gpu2d_axi_clk);

clk_enable(openvg_axi_clk);

}

udelay(150);

/* enable power up request */

reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);

__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);

/* power up request */

reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);

__raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET);

/* Wait for the power up bit to clear */

while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2)

;

/* Enable the Brown Out detection. */

reg = __raw_readl(ANA_MISC2_BASE_ADDR);

reg |= ANADIG_ANA_MISC2_REG1_BO_EN;

__raw_writel(reg, ANA_MISC2_BASE_ADDR);

#ifndef CONFIG_MX6_INTER_LDO_BYPASS

/* Unmask the ANATOP brown out interrupt in the GPC. */

reg = __raw_readl(gpc_base + 0x14);

reg &= ~0x80000000;

__raw_writel(reg, gpc_base + 0x14);

#endif

pu_is_enabled = 1;

if (get_clk) {

if (!cpu_is_mx6sl()) {

clk_disable(gpu3d_clk);

clk_disable(gpu3d_shade_clk);

clk_disable(vpu_clk);

}

clk_disable(gpu2d_clk);

clk_disable(gpu2d_axi_clk);

clk_disable(openvg_axi_clk);

}

return 0;

}

[RobinGong]

Hi  William,

     Can you share more detail information as below about your board?

1. Is there   external LDO power rail for VDDARM/VDDSOC/VDDPU? If no, you have to set  'LDO_MODE_ENABLED' which mean internal anatop regulator enabled. If yes, you can use  'LDO_MODE_BYPASSED'   so that bypass internal anatop regulator to reduce power number. Of course , you should provide the right external regulator name for 'gp_reg_id'/'soc_reg_id'/'pu_reg_id' and so on. You can set the LDO mode (enable_ldo_mode)in the board level file of pmic, such as arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c .  The default value is "LDO_MODE_ENABLED".

2. From your information, I guess you want to use LDO BYPASS mode and there is external power rail or pmic in your board, right? If not, I think the LDO patch shouldn't cause “COULD NOT SET GP VOLTAGE!!!!”.  If yes, you'd better  do some change in your pmic regulator driver as what pfuze did in the patch.

[williamtung]

Hi Yibin,

1. There's no external LDO on our board. I didn't set 'LDO_MODE_ENABLED' since it's enabled by default.

2. I'll re-apply the patch to a clean build and check again.

[mtx512]

The "COULD NOT SET GP VOLTAGE" is caused by double initialisation of the CPU regulator in the code "mx6_cpu_regulator_init(); "

[lily_zhang]

Thanks to share the finding. We didn't reproduce the failure and not sure whether we are using the same code baseline. Can you please clarify more details bout "double initialisation of the CPU regulator in the code "mx6_cpu_regulator_init(); "?

[lily_zhang]

Hello, William:

You mentioned after applying for FSL LDO patch, you see new error. Can you please share the patch you applied?