FPGA Configuration Over EIM Bus

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FPGA Configuration Over EIM Bus

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tom1
Contributor II

Hi,

     I would like to configure a Xilinx FPGA, using SelectMAP configuration mode, over the EIM bus on a i.MX6 D/Q.  Are there any application notes or any information on how to set up the EIM bus to accomplish this?

Thanks,
Tom

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danielleloader
Contributor III

Hi Tom,

We've managed to achieve a byte-wide boot of a Spartan 6 device using the EIM, it wasn't too hard.

The main thing to get right is the byte and bit order. The iMX6 deals in 32bit memory locations, so EIM writes are always 32 bit. If your bus is byte-wide then this means you have to pack each write with 4 bytes of your FPGA design. We also found we had to reverse the bit order.

A couple of tips:

  • Route your FPGA's chip-select line to a GPIO so you can select it for the whole configuration period (rather than it being gated)
  • Make sure the EIM module is out of reset: 0x20D000 == 0x0
  • Enabled EIM clocks in CCM Register 6 (CG5)
  • Modify the default values of EIM_CS0GCR1, EIM_CS0RCR1, EIM_CS0RCR2 and EIM_CS0WCR1. We found these were pretty close to what we need already.
  • Get the timing of PROG_B and INIT_B right, based on Xilinx's FPGA configuration guides. Essentially you need to wait a few microseconds after releasing reset before you configure the device.

Hope that helps.

Danielle

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tom1
Contributor II

Hi Danielle,

Are you using synchronous EIM mode and BCLK to clock in the configuration data?

Or, asynchronous mode with a free-running clock connected to CCLK?

If you are using synchronous mode, won’t the BCLK for the address phase(ADV low) clock in incorrect data?

Thanks,

Tom

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danielleloader
Contributor III

Hi Tom,

We're using asynchronous mode with EIM_BCLK output connected to the FPGA.

Dani

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tom1
Contributor II

Hi Danielle,

From you postings, I gather that you were using asynchronous mode with BCLK tied to CCLK and BCLK was continuously running.

The confusing part is your comment about chip select. It is my understanding that you used a GPIO to control the CSI_B input of the FPGA during configuration and kept it low during the loading of the configuration data.

If that is correct, won’t the free-running CCLK clock in any data that is on the EIM data bus while CSI is low? For example, the CCLK will be running, and CSI will be low, during the address phase of the asynchronous access where the data may be invalid.

Thanks,

Tom

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