Exposing IMX8MQ UART3 CTS line as a GPIO

[pradeep2481]

Hi,

I want to make the UART3 CTS line as a GPIO so that the CTS line can be controlled using the GPIO.

I have gone through the device tree file but did not get enough information to do the changes.

Can you please help me in this?

Thanks in advance.

Best regards,

Pradeep

[pradeep2481]

Thank you so much for the nice explanation.

[pradeep2481]

Thanks for your quick response.

From the device tree file pins for uart3 are defined as follows.

pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};

from the line "MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49" what I understood is that the CTS line is used for Enhanced Configurable SPI. So I would like to remove this functionality of the CTS line and instead use it as a GPIO pin. But I did not find a GPIO definition for CTS (in the file include/dt-bindings/pinctrl/pins-imx8mq.h) which I can use it in the device tree file. So I am not getting how I can set it in the device tree file. 

Best regards,

Pradeep

[jimmychan]

Which pin are you using for the UART3 CTS? you can set it to GPIO in the device tree file.

[pradeep2481]

Thanks for your quick response.

From the device tree file pins for uart3 are defined as follows.

pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};

from the line "MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49" what I understood is that the CTS line is used for Enhanced Configurable SPI. So I would like to remove this functionality of the CTS line and instead use it as a GPIO pin. But I did not find a GPIO definition for CTS (in the file include/dt-bindings/pinctrl/pins-imx8mq.h) which I can use it in the device tree file. So I am not getting how I can set it in the device tree file. 

Best regards,

Pradeep

[pradeep2481]

Thanks for your quick response.

From the device tree file pins for uart3 are defined as follows.

pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};

from the line "MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49" what I understood is that the CTS line is used for Enhanced Configurable SPI. So I would like to remove this functionality of the CTS line and instead use it as a GPIO pin. But I did not find a GPIO definition for CTS (in the file include/dt-bindings/pinctrl/pins-imx8mq.h) which I can use it in the device tree file. So I am not getting how I can set it in the device tree file. 

Best regards,

Pradeep

[jimmychan · Accepted solution]

Hello,

MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49

ECSPI1_MISO is the real pin on the chip. (this is ball B4, you can check the pin assignments in the datasheet for details).

UART3_DCE_CTS_B is one of the IOMUX functions of the pin ECSPI1_MISO. The details can be found in the Reference Manual Chapter 8.2.5.123 SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO)

0x49 is the PAD Control setting of the pin such as Pull-up enable, Slew rate. The details can be found in the Reference Manual Chapter 8.2.5.277 SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO)

Basically, you can search the pin ECSPI1_MISO in the imx8mq-pinfunc.h. Then you will find the GPIO function for the ECSPI1_MISO is MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8.

So in the device tree file, you can modify like this:

pinctrl_uart3: uart3grp {
fsl,pins = <
                MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
                MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
-               MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49             

+              MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x19
                MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
                MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;