Error in bringing up Parallel NOR Flash using Sabre AI Wiemnor Uboot

[nishad_kamdar]

Hello all,

I have designed a custom IMX6q board which resembles the SabreAI.

I was able to port U-Boot on my processor via the WiemNor (Parallel NOR Flash).

I have attached the Snapshot.

As you can see uboot has been able to bring up the DDR and Uart.

However, i have loaded the kernel in Parallel Nor flash.

As you can see, the Uboot has not been able to bring the NOR Flash up.

Which is why it is not able to pick the Kernel up from the default base 0x8080000 to 0x10800000.

My parallel NOR flash is Spansion S29GL01GP.

I am running it in 16 bit mode.

I have connected the data lines to the Lower data bits of the EIM data bus in contrast to the SABRE AI board where the NOR flash is connected to the Higher order data bus.

I have modified the IOMUX in mx6_sabreauto.c (I am Using the Sabre AI Weimnor Uboot).

Kindly suggest the additional modifications to be done to bring the NOR Up.

Regards,

nishad

[alejandrolozan1]

Hi,

Can you show the connections? and if you modified something to the EIM module. That I assume you changed the DSZ field in order to  choose the correct 16bit data.

Best Regards,

Alejandro

[nishad_kamdar · Accepted solution]

Hi,

sorry for the delay in reply,

I got it working,

I had to modify these register settings for the NOR to work along with the IOMUX

Yes I Modified the DSZ settings

static void weim_norflash_cs_setup(void)

{

    writel(0x00000020, WEIM_BASE_ADDR + 0x090);

    writel(0x00610081, WEIM_BASE_ADDR + 0x000);

    writel(0x00000001, WEIM_BASE_ADDR + 0x004);

    writel(0x1c020000, WEIM_BASE_ADDR + 0x008);

    writel(0x00000000, WEIM_BASE_ADDR + 0x00c);

    writel(0x0804a240, WEIM_BASE_ADDR + 0x010);

}

#if defined CONFIG_MX6Q

iomux_v3_cfg_t nor_pads[] = {

   MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,

  MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,

  MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,

  MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,

  MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,

  MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,

  MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,

  MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,

  MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,

  MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,

  MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,

  MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,

  MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,

  MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,

  MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,

  MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

  MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,

  MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,

  MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,

  MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,

  MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,

  MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,

  MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,

  MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,

  MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24,

  MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25,

  MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,

  MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,

  MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,

  MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0,

  MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1,

  MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2,

  MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3,

  MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4,

  MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5,

  MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6,

  MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7,

  MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8,

  MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9,

  MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10,

  MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11,

  MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12,

  MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13,

  MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14,

  MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15

};

[rkp]

Dear Nishad,

Could  you please tell me the size of UBoot and kernel that you flashed to parallel NOR ?

Thanks and Regards,

Roopesh