Enable 4 Lane MIPI Camera fail

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Enable 4 Lane MIPI Camera fail

582 Views
Contributor III

Hi Sir,

In SabreSD board, ov5640_mipi have 2 lane and connected to MIPI CSI port.

In Customer board and test a custom mipi camera with two modes:

1. 1280x720@30fps 2lanes

2. 1920x1080@30fps 4lanes

Customer setting MIPI DPHY clock to match camera sensor clock.


Customer set lane=4 can get below log:

mipi csi2 can not reveive data correctly!


According the AN5305 doc, setting the MIPI DPHY clock (CSI2_PHY_TST_CTRL1)


ex: https://community.nxp.com/thread/307065#328301


- mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);
+ mipi_csi2_write(info, 0x00000008, CSI2_PHY_TST_CTRL1);


dtsi:

&mipi_csi {
status = "okay";
ipu_id = <0>;
csi_id = <1>;
v_channel = <0>;
lanes = <2>; -> change to 4
};

Do you have any ideas about this? Thank you very Much.

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3 Replies

25 Views
Contributor II

Hi Sir:

I try to porting the tc358743 module (HDMI to MIPI) on  i.MX6Q  with Android 6.0.1.

In current, The mode 1280x720@60fps 2lanes are ready,

but fail to enable 1920x1080@60fps 4lanes mode.

 I set the lanes = <4> and the CSI2_PHY_TST_CTRL1 =0x30 but still get error log:

mipi csi2 can not reveive data correctly!

The registers status are below:

MIPI_CSI_PHY_STATE : 0x300 or 0x330

MIPI_CSI_ERR1 : 10000010


Do you have any ideas about this?

25 Views
NXP TechSupport
NXP TechSupport

Hi, Jimmy Chen,

   The issue should be related to the MIPI Clock setting, customer's log "mipi csi2 can not reveive data correctly!", means data not correct, that is data has been received, but not correct.

   So my advice is try to modify the clock root of MIPI CSI2 module.

   On the link, https://community.nxp.com/thread/307065#328301 , you can see Gao Jianzhong's experience :

pastedImage_1.png

   So suggest you'd better try to modify MIPI CSI2's clock ROOT.  you can find source code of  i.MX6Q's clock tree at path "arch/arm/machimx/" or "drivers/clk/..."

Have a nice day!

NXP TIC weidong sun

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25 Views
Contributor III

Hi Wigros Sun,

We modify axi_clk rate from 264M to 528M as below setting.

imx_clk_set_rate(clk[IMX6QDL_CLK_AXI], 528000000);

 

It's can read AXI_PODF field set to divide by 1 (original setting is 2)

root@dmsst17_6dq:/data # ./memtool -32 0x20C4014 1                         

 

0x020C4014:  00008D00

 

But the mipi camera still not worked and get error log.

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