ENGcm04758 ARM: Incorrect L2 cache eviction can occur when L2 is configured as an inner cache

[MattiasBarthel1]

hi, I m trying to find the commit that does this::

 The software workaround is to disable write allocate in the Level 2 cache in the bootloader. So no
condition is to trigger this issue. This workaround has performance penalty.

In the https://github.com/nxp-imx/uboot-imx.git 

thank you,

Mattias

[Bio_TICFSL]

Hello,

Yes is the u-boot-2009.01 version

Regards

[MattiasBarthel1]

Hi @Bio_TICFSL  thanks for your reply.

Could you specify the exact commit from that tag, please?

Regards,
Mattias

[MattiasBarthel1 · Accepted solution]

I guess I have found it. 

 

commit 64fdf452a85718935d82416d141be144b262c542
Author: Stefano Babic <sbabic@denx.de>
Date: Wed Jan 20 18:19:32 2010 +0100

MX51: Add initial support for the Freescale MX51

The patch add initial support for the Freescale i.MX51 processor
(family arm cortex_a8).