Hi,
I am planning on interfacing an i.MX6D/Q to an FPGA using the EIM bus. To that end, it would help to have either a Verilog or VHDL model to drive the EIM, in simulation, to simulate EIM read/write accesses from the i.MX to the FPGA.
Does Freescale offer any Verilog or VHDL bus functional models for the EIM bus?
If not, do you know of any third-party or open source BFMs?
Thanks,
Tom
