EDAC Driver for IMX8DXL

[chanks]

Is there a Linux EDAC driver that can be used with the IMX8DXL?  The reference manual lists out the ECC registers for the IMX8DXL, but are the DDRC registers available on the A35 cores?

The reference manual just says the DDRC Base address is 0h.  Is this correct?

I'm trying to use the Synopsys EDAC driver.

• Will this driver work with the IMX8DXL DDRC?
• If it will work, what value should I put in the reg entry in the device tree to get this to work?

[chanks]

I saw in the reference manual that there is a DRC0 in the Db Memory Map, but also it says that the Db Memory map is accessible only by the SCU. Is this the DDR Controller?

I tried the following in my device tree, but this produces a kernel panic:

&ddr_subsys {
        edacmc: memory-controller@5c000000 {
                compatible = "snps,ddrc-3.80a";
                reg = <0x5c000000 0x10000>;
                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* Correctable error */
                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, /* Uncorrectable error */
                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; /* Address Channel Error */
               interrupt-names = "ecc_ce", "ecc_ue", "ecc_ap";
        };
};

[Manuel_Salas]

Hello, 

Unfortunately, there is not a specific EDAC linux driver for i.mx8dxl.

You can refer to the imx8-ss-ddr.dtsi, there is defined the ddr_subsys node for i.MX8.

Also the imx8dxl-ss-ddr.dtsi.

Those dtsi are defined on the imx8dxl.dtsi.

Best regards,

Salas.

[chanks]

I've checked out those dtsi files before but it's not really helpful for the issue. Is the DDRC accessible from the A cores? If so, what is the memory address? I think I can adapt the existing EDAC driver to work if I only knew the correct address.