ECSPI problem on M7 core of the IMX8MP

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ECSPI problem on M7 core of the IMX8MP

740 次查看
teleportboy
Contributor I

On the board with Cortex-M7, ADS8028 is connected via SPI. However, attempts to communicate with the ADS8028 device end in failure. I based my approach on the spi_polling example from the SDK. I configured the multiplexing correctly, according to the .dts file. But after sending a specific sequence of bits according to the ADS8028 datasheet via SPI, the RX buffer only records 0x0 or some garbage, now what I expect. Interestingly, the same behavior occurs even if the multiplexer is deliberately misconfigured or not configured at all.

What could be the problem?

Configuring ecspi from the .dts file:

 

 

pinctrl_ecspi2: ecspi2grp {
	fsl,pins = <
		MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK		0x82
		MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI		0x82
		MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO		0x82
		MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x82
		MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       	0x146
	>;
};

 

Initializing ECSPI code:

    /* Master config:
     * masterConfig.channel = kECSPI_Channel0;
     * masterConfig.burstLength = 8;
     * masterConfig.samplePeriodClock = kECSPI_spiClock;
     * masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
     * masterConfig.chipSelectDelay = 0;
     * masterConfig.samplePeriod = 0;
     * masterConfig.txFifoThreshold = 1;
     * masterConfig.rxFifoThreshold = 0;
     */
    ECSPI_MasterGetDefaultConfig(&masterConfig);

    masterConfig.channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
    masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;

    ECSPI_MasterInit(EXAMPLE_ECSPI_MASTER_BASEADDR, &masterConfig, ECSPI_MASTER_CLK_FREQ);

 

teleportboy_0-1705506342960.pngteleportboy_1-1705506509842.png

 



 

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723 次查看
JosephAtNXP
NXP TechSupport
NXP TechSupport

Hi,

Thank you for your interest in NXP Semiconductor products,

DTS file reserves pins for Linux (Cortex-A) operation, if Cortex-M uses the pin or it's unused, it's not "okay" in DTS.

You need to remove ECSPI pins in DTS, the pins are initialized in pin_mux.c, see below:

/* FUNCTION ************************************************************************************************************
 *
 * Function Name : BOARD_InitPins
 * Description   : Configures pin routing and optionally pin electrical features.
 *
 * END ****************************************************************************************************************/
void BOARD_InitPins(void) {                                /*!< Function assigned for the core: Cortex-M7F[m7] */
    IOMUXC_SetPinMux(IOMUXC_ECSPI2_MISO_ECSPI2_MISO, 0U);
    IOMUXC_SetPinConfig(IOMUXC_ECSPI2_MISO_ECSPI2_MISO, 
                        IOMUXC_SW_PAD_CTL_PAD_DSE(2U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);

Regards

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