Does i.MX95 support LPDDR5X memory?

[jimmychang]

Does i.MX95 support LPDDR5X memory?

If MR8[1:0]=01 or MR5 ID is not in your support list

How do i.MX95 check supported or not? check MR register?

[jimmychang]

Thanks for your quickly apply.

[jimmychang]

As you said "MR8[1:0] = 01 means the device is LPDDR5X-only "

MR8[1:0]=00 support LPDDR5, MR8[1:0]=01 support LPDDR5x.

So what should MR8[1:0]=?? support LPDDR5 and LPDDR5x ?

[yipingwang · Accepted solution]

Per JEDEC LPDDR5/LPDDR5X definitions:

MR8[1:0]	Meaning
00b	LPDDR5 capable
01b	LPDDR5X capable
10b	Reserved
11b	Reserved

The problem is that MR8 only reports the mode family implemented by the device, but it does not tell you whether the device can also operate in the other mode.

Example

Consider a Samsung part advertised as LPDDR5X.

The device may:

• Be an LPDDR5X device that is backward compatible with LPDDR5.
• Power up reporting MR8[1:0]=01.
• Still be fully usable on i.MX95 because it supports LPDDR5 operation.

NXP's compatibility guide explicitly mentions that many memories marketed as "LPDDR5X" are actually backward-compatible with LPDDR5 and can therefore be used with i.MX95.

Then MR8[1:0] is an identification field, not a capability bitmap . So a dual-capable / backward-compatible LPDDR5X-marketed device normally has to be checked from the DRAM datasheet , not inferred from a special MR8 “both” code.

[yipingwang]

• Yes, i.MX95 can work with many LPDDR5X devices, but only if those devices also support LPDDR5 backward-compatibility mode.
• i.MX95 does NOT support LPDDR5X-only devices. 
• Therefore, checking whether a memory is supported is not simply a matter of looking at MR8[1:0] or MR5 vendor ID alone.

• MR8[1:0] = 01 means the device is LPDDR5X-only → treat it as not supported for i.MX95, because NXP states LPDDR5X-only devices cannot be used.
• MR5 manufacturer/device ID is not in NXP’s validated list → it is not validated by NXP , but that alone is not the same as “impossible.” You still need to confirm from the memory datasheet that the part supports LPDDR5 mode and matches the supported density/organization/timing constraints, then validate it in the board design.