Documentation Errors and the System-Reset-Controller (SRC) Module... missing pads on the iMX6

[austin-]

In the i.MX 6Dual/6Quad Applications Processor Reference Manual (Document Number: IMX6DQRM, Rev. 0, 11/2012), a pad (RESET_IN_B) is called out in section 10.4.1.4.3.3.  It mentions that one can turn on and off the PMIC supplies to the SoC by setting SNVS_LP DP_EN to “1” which allows access to the PMIC_ON_REQ pad directly.  I can find no such pad (RESET_IN_B), nor can I find SNVS_LP DP_EN.  This pad (RESET_IN_B) is also referenced in section 11.4.2 as being the pad to which the on/off button should be attached.  Is it safe to assume it should be attached to the ONOFF pad instead?

I would like to be able to have the SoC control the PMIC (so it can execute the low power modes), but also be able to use a button to force a hard reset (as mentioned in section 59.2.1) should the SoC become unresponsive.  I am using the PF0100 as the PMIC and cannot determine by which method described in section 59 this can be accomplished.

On both Figure 59-2 and 59-3 (IMX6DQRM) there is an input called RST that is NAND’d and NOR’d with the ONOFF input.  To what PAD or signal does this connect?

Assume the PMIC has been connected as suggested in IMX6DQSDLHDG (Hardware Development Guide for i.MX6), Rev0, 10/2012.  The PF0100 defaults to PWRON_CFG = 0, the level trigger, but in the Power Mode transitions table 59-1 (IMX6DQRM) detailing the flow with the PMU in control, it appears that all of the behavior of the SoC when it is in control is assuming that the PF0100 has PWRON_CFG=1.  Is this true?

In the "Emergency On to OFF by button", Table 59-1 (IMX6DQRM), (which is the case in which I am most interested) #3 implies that a ‘1’ on pmic_en_b will turn off the PF0100.  This can only be true if the button press (to GND) has been routed through to the PMIC_ON_REQ pad so that the output to the PF0100 has been held low for longer than 4 seconds.  Is this true?  Does this behavior require any special register control (i.e. the previously mentioned difficult to find SNVS_LP DP_EN)?

I would love to know how to get a PMIC and iMX6 which are both in deep sleep modes to perform a power-on-reset.

[Yuri]

Some clarifications may be found here

Re: mx6Q TO1.2 Reset

[austin-]

The link you have so kindly provided reports, "Unauthorized, Access to this place or content is restricted..."  Is there another public location with that information or maybe that thread could be made public?

Thanks,

Austin

[RodBorras]

Austin,

Several of the pins that you cannot find are actually alternate functions of standard pins (ONOFF and TEST_MODE).

Given that TEST_MODE is really only meant for Freescale Manufacturing & Test purposes (and should be grounded in all other cases), and that these pins only take their secondary role when they are used in this special way, we will be removing references to this functionality in the next revision of the Reference Manual.

That is the gist of what Yuri's link says.

Regards,

Rod.

[austin-]

I greatly appreciate the response, but I can't help but feel that you didn't read the original post.

The questions are:

Where is the SNVS_LP DP_EN?  Is it a pad? Is it a register?  What name does it go by the IOMUX tables?

Where is the RESET_IN_B pad?  Or what name is the RESET_IN_B known by in the IOMUX tables?

In Figure 59-2 and 59-3 (IMX6DQRM), where or what is the signal named RST in the figure?

In the "Emergency On to OFF by button", Table 59-1 (IMX6DQRM), item #3, how is the button press routed through with respect to PMIC_ON_REQ?

I have a PCB waiting to go to fab because we can't get any resolution on how to connect a button, the PF0100, and the iMX6's SRC pads.  We need to ensure that if the PF0100 is in a low power\sleep state and the iMX6Q is in a sleep state and everything goes wrong, we can reset the device.

Regards,

Austin

[Yuri]

Please look at section 6.10.15 "SNVS_LP Control Register (SNVS_LPCR)" of the Security Reference Manual for i.MX6.

Security Reference Manual for i.MX 6

[Yuri]

Some clarifications :
"So, the RST signal shown in the 6DQ reference manual, Rev, Figures 59-2 and 59-3 is actually the TEST_MODE pin. In normal usage the test mode pin is always supposed to be low. When the TEST_MODE pin is high, it enables an alternate function of ONOFF which is RESET_IN_B. The datasheet specifies that TEST_MODE should be tied to ground or floated (because it has an internal pull-down). So this is why you get no reset from this configuration. With TEST_MODE always low, the ONOFF button/signal does not pass through as a reset to the SRC."