Designing a schematic for NXP imx6ull MCIMX6Y2DVM09AB

[Nikunj_Solanki]

Hi everyone,

I'm designing a schematic based on the NXP imx6ull MCIMX6Y2DVM09AB processor and I'm looking for some help from the NXP community.

Specifically, I'm interested in the following areas:

1. Power supply scheme: How many different voltages are required for the imx6ull MCIMX6Y2DVM09AB processor? What are the typical voltage levels and current requirements for each voltage?
2. Power supply sequence: What is the recommended power supply sequence for the imx6ull MCIMX6Y2DVM09AB processor? Are there any specific timing requirements or considerations?
3. Component selection: How do I select the right components for the power supply section? What are the key factors, such as voltage regulators, capacitors, and inductors?
4. Schematic design guidelines: Are there any specific guidelines or best practices for designing a schematic for the imx6ull MCIMX6Y2DVM09AB processor?

I would greatly appreciate any advice or insights you can provide. I appreciate any help you can provide.

Best regards,

[Nikunj_Solanki]

Can you please verify the PMIC Parts number?
MC32PF1550A0EP

[Rita_Wang]

Yes, it is PMIC with 1A Li+ Linear Battery Charger | NXP Semiconductors

[Nikunj_Solanki]

Thank You so much for your support!

[Nikunj_Solanki]

Thank You so much for your response.
I am using DDR3L SDRAM so, any special power supply required to manage DDR3L in the NXP datasheet mentioned is 1.35V.

[Rita_Wang]

Yes, for DDR3L the power is 1.35, You can use the DDR3L on the i.MX6ULL just following the Hardware Development Guide for the i.MX 6ULL Applications Processor.

[Nikunj_Solanki]

Yes, I want to choose to use PMIC, Please suggest.

[Nikunj_Solanki]

Yes, I want to choose PMIC, so please recommend and can you please explain to me a power on/off sequence?

[Rita_Wang]

Details you can see in our datasheet:

Rita_Wang_0-1729738996362.png

For the design with PMIC, I email to you.

[Nikunj_Solanki]

I am using DDR3L and am a little bit confused about the VDD_SOC_IN voltage configuration. According to a datasheet, its range is from 1.15V to 1.3V. So, which voltage is suitable for my application?

[Rita_Wang]

PMIC can out put what the voltage you want for the VDD_ARM_SOC_IN, so you do not care about it, if you choose the PMIC in your design.

[Nikunj_Solanki]

But, I don't know exactly which voltage is chosen for VDD_SOC_IN.

Does it affect DDR3L if I choose 1.05V or 1.225V?

[Rita_Wang]

For the VDD_SOC_IN it need 1.275 to 1.5 for 528MHz for A7 core work, and  1.375 to 1.5 for 900MHz for A7 core work.

Rita_Wang_0-1730181519830.png

From the design I share to you, you can see that for the VDD_SOC_IN it is supply from the SW1 of the PF1550.

Rita_Wang_0-1730189285660.png

Rita_Wang_1-1730189349782.png

From the PF1550 datasheet you can see that the SW1 can supply:

SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps

So it can supply what the VDD_SOC_IN need, so you do not know what the exactly the value it is.

PMIC with 1A Li+ Linear Battery Charger | NXP Semiconductors

PF1550, Power management integrated circuit (PMIC) for low power application - Data sheet

Rita_Wang_2-1730189440591.png

For the DDR3L, the Voltage is 1.35V, and the power for the DDR is from NVCC_DRAM power, DDR will effect by it:

Rita_Wang_0-1730168312112.png

[Nikunj_Solanki]

Thank You so much for your support.

[Rita_Wang]

You can refer to our reference design and hardware design guide document, and following our datasheet, following the power on/off sequnce.

Do you need to choose use PMIC IC or not?

[Nikunj_Solanki]

Please share reference design file and suggest PMIC IC