DDR3 routing for DRAM_A[15:0] in i.MX6DQ.

[keitanagashima]

Hello.

I have questions about DDR3 routing rule.

Refer to "Table 3-3. DDR3 routing by byte group" in Hardware Development Guide for i.MX6 Rev. 1.

"DRAM_A[15:0] Min : Clock (min) – 200"

[Q1]

Where JEDEC (or i.MX6) timing specification does this rule influence?

(Only Address output setup time? Address output hold time?)

[Q2]

I'd like to know the background to have decided that is "Clock (min) – 200".

Best Regards,

Keita

[Yuri]

  Note, the (asymmetrical) requirements [in Table 3-3 (DDR3 routing by

byte group)], say, for signals of Address and Command group to be shorter than

the clock (min = clock-200, max = clock) relate to specifics of i.MX6 implementation
(say, for i.MX6 address setup and hold  timings are not symmetrical).

Have a great day,
Yuri

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[keitanagashima]

Hi Yuri,

[Q1]

If my customer violate the below rule, which parameter does it impact?

> signals of Address and Command group to be shorter than

> the clock (min = clock-200, max = clock) relate to specifics of i.MX6 implementation

[Q2]

Do you know why did freescale define the Address line with "min = clock-200"?

I'd like to know the background of this rooting rule.

(This question looks difficult...)

Best Regards,

Keita

[Yuri · Accepted solution]

Keita, hi !

  Basically, the best approach - to use simulation technique for PCB design.

In the same time, general rules may be provided for customers to simplify their

PCB considerations, but note, for assurance such rules are very strong.

  Some considerations below about address and clock recommendations, hope,
help to clarify it.

  IMX6 output DRAM address and clock signals, assuming address should be
latched at clock edge in the center of address assertion. In practice, because
of PCB trace delays, it is possible to vary clock edge position. But setup an hold
timings provide available most right and left locations of the clock edge.
When setup and hold timings are not the same, it would be preferable to
restrict clock varying for one direction. 

From the recent Datasheet :

DDR6 (Address output setup time, tIS) = 500 ps

DDR7 (Address output hold time, tIH) = 400 ps

    So, basic concept is that clock and address traces should be very close each
other to avoid timing problems because of signal delays ; but we can allow
some shift to right (on the figure) for the clock, since hold time is less than
setup. 200 mils mean about 30 ps of delay (6’’ ~ 1 ns), which is 1/3 of
(tIS – tIH) – for assurance. 

Regards,

Yuri.