DDR3 configuration for imx6q processor

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DDR3 configuration for imx6q processor

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sanketparekh
Contributor II

Hi.

Greetings.

We are working on imx6q processor, our custom board have one DDR3 of 512MB. So i have configured DDR for imx6q processor from I.MX6DQSDL DDR3 Script Aid V0.10.xlsx. When i load the u-boot with configured DDR on our custom board, u-boot image will not flash properly.

iMX6Q: MCIMX6Q6AVT08AD

DDR3: MT41K256M16TW-107 AAT:P

DDR type is DDR3   
Data width: 16, bank num: 8  
Row size: 15, col size: 10  
Chip select CSD0 is used   
Density per chip select: 512MB

We are generation DDR3 configuration from "I.MX6DQSDL DDR3 Script Aid V0.10.xlsx" file and using "DDR_Stress_Tester_V1.0.2" tool we are configuring and calibrating the DDR3 on custom board.

Is there any register value mismatch for DQS?

Is there any sequence we are missing?

So please give me some solution for the same.

Configuration file are present in attachments.

LOG:

============================================  
        DDR Stress Test (2.6.0)   
        Build: Aug  1 2017, 17:33:25  
        NXP Semiconductors.  
============================================  
 
============================================  
        Chip ID  
CHIP ID = i.MX6 Dual/Quad (0x63)  
Internal Revision = TO1.5  
============================================  
 
============================================  
        Boot Configuration  
SRC_SBMR1(0x020d8004) = 0x00005878  
SRC_SBMR2(0x020d801c) = 0x3a000001  
============================================  
 
ARM Clock set to 800MHz  
 
============================================  
        DDR configuration  
BOOT_CFG3[5-4]: 0x00, Single DDR channel.  
DDR type is DDR3   
Data width: 16, bank num: 8  
Row size: 15, col size: 10  
Chip select CSD0 is used   
Density per chip select: 512MB   
============================================  
 
Current Temperature: 31  
============================================  
 
DDR Freq: 396 MHz   
 
ddr_mr1=0x00000004  
Start write leveling calibration...  
running Write level HW calibration  
Write leveling calibration completed, update the following registers in your initialization script  
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F  
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F  
Write DQS delay result:  
   Write DQS0 delay: 31/256 CK  
   Write DQS1 delay: 31/256 CK  
 
Starting DQS gating calibration  
. HC_DEL=0x00000000    result[00]=0x00000011  
. HC_DEL=0x00000001    result[01]=0x00000011  
. HC_DEL=0x00000002    result[02]=0x00000011  
. HC_DEL=0x00000003    result[03]=0x00000011  
. HC_DEL=0x00000004    result[04]=0x00000011  
. HC_DEL=0x00000005    result[05]=0x00000011  
. HC_DEL=0x00000006    result[06]=0x00000011  
. HC_DEL=0x00000007    result[07]=0x00000011  
. HC_DEL=0x00000008    result[08]=0x00000011  
. HC_DEL=0x00000009    result[09]=0x00000011  
. HC_DEL=0x0000000A    result[0A]=0x00000011  
. HC_DEL=0x0000000B    result[0B]=0x00000011  
. HC_DEL=0x0000000C    result[0C]=0x00000011  
. HC_DEL=0x0000000D    result[0D]=0x00000011  
ERROR FOUND, we can't get suitable value !!!!  
dram test fails for all values.   
 
Error: failed during ddr calibration

Thank you.

Sanket

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igorpadykov
NXP Employee
NXP Employee

Hi Sanket

what about other memory tests, had they passed, as

"DQS gating calibration" errors are no fatal and board still may work well.

DDR tester errors are described in i.MX6 DRAM Port Application Guide-DDR3 on

Freescale i.MX6 DRAM Port Application Guide-DDR3 

and these errors may be caused board noise and not implementing layout rules

described in sect.3.5 DDR routing rules i.MX6 System Development User’s Guide

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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riteshpatel
Contributor II

Hi Igor,

We have verified all the design guidelines shown in the iMX6Q hardware design guide and it is as per recommendations.

I have attached three files for your review as below:

  1. Schematic showing 16-bit interface between 512MB Automotive grade DDR3L memory and iMX6Q
  2. DDR3 script file for DDR configuration:  I.MX6DQSDL DDR3 Script Aid V0.10, used to generate DDR configuration for our board. Can you confirm we are using correct version?
  3. Our custom board DDR memory ( MT41K256M16TW-107 AAT:P) link: 

      https://www.micron.com/~/media/documents/products/data-sheet/dram/ddr3/4gb_automotive_ddr3l.pd... 

Can you generate the DDR configuration from above details? This way we can verify if we are doing any mistake in configuration file generation.

We are performing following steps for DDR bring-up:

  • Generate basic list of parameters from DDR configuration script excel (It is written in the script that it is required to run DDR stress tester first to get the correct DCD settings)
  • Calibrate it with DDR stress tester tool over windows and doing DCD settings and it should be passed successfully
  • Integrate the above parameters in the *.cfg file and load the DCD along with the u-boot.

After performing above steps too we are not successfully completed DDR calibration and U-boot loading.

Greatly appreciate your earliest response. 

Thanks,

Ritesh.

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igorpadykov
NXP Employee
NXP Employee

Hi Sanket

 

what about other memory tests, had they passed.

Best regards
igor

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riteshpatel
Contributor II

Other tests log file

============================================
DDR Stress Test (2.6.0)
Build: Aug 1 2017, 17:33:25
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00005878
SRC_SBMR2(0x020d801c) = 0x3a000001
============================================

ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================


DDR Stress Test Iteration 1
Current Temperature: 42
============================================

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000000
Data was: 0xffffffff
But pattern should match address
Error: failed to run stress test!!!

addr=0x10000000,data=0x50505050

Success to write address 0x10000000

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x10000000: 0x50505050
memory read is done

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igorpadykov
NXP Employee
NXP Employee

Hi Ritesh

if there no any tests passed fine (note write leveling calibration passes even ddr interface is not
working at all), it may mean that ddr interface is not working. Please check hardware using
i.MX6 System Development User’s Guide
https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Regarding DQS gating calibration, one can try to set WALAT=1 in MMDCx_MDMISC register.
Also suggest to check signals with oscilloscope: place a probe on DQ0 and DQ8 to
see if either trace goes high during the DQS gating calibration.
Check to see that RESET_B is going high, if SDCKE0 is going high.
Place a probe on SDCLK_0 and/or SDCLK_0_B and make sure you see
a clock signal on both.
As this ddr is similar to i.MX6Q Sabre SD memory (MT41K128M16JT) one can
start with its cfg file (just adusting row, bus width settings) on
uboot/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:
uboot-imx.git - Freescale i.MX u-boot Tree 

Best regards
igor

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riteshpatel
Contributor II

Hi Igor,

Thank you for the reply.

  1. We have checked with  WALAT=1, and checked RESET_B, SDCKE0 and SDCLK_0_B which is constant low. We have also checked that there is no ground shorting on the pins.
  2. We have also checked DRAM_RESET, DRAM_CLK0, SDCKE0  that pins are also low on our board at the time of flashing as well as doing the DDR related tests.

  3. We have checked DDR_VREF = 0.75V, and 1.5V voltage is proper.
  4. For configuration file as per your suggestion we have modified the configuration file.

Can you please help us to 

  1. Please review the DCD configuration file "MT41K256M16TW-107.cfg" .
  2. Can you please provide more debug points on hardware front?
  3. Is it possible to debug this issue with JTAG to know the memory written in the DDR as well as to check whether the processor bootrom is stuck somewhere or not? (We have checked on the J-Link that imx6q is supported by it.)

Greatly appreciate your support and further steps in debugging this.

Regards

Ritesh.

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igorpadykov
NXP Employee
NXP Employee

Hi Ritesh

most probably hardware is not working, please refer to

i.MX6 System Development User’s Guide for checking board hardware

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Best regards
igor

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riteshpatel
Contributor II

Hi Igor,

We have already verified that schematics and layout related recommendations/rules mentioned in this document. 

1) Is it possible due to wrong DCD configuration this pins are low?

2) Please provide inputs for next debug approaches.

Regards,

Ritesh.

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igorpadykov
NXP Employee
NXP Employee

Hi Ritesh

1. you can start with default dcd configuration provided in nxp bsps

(just adusting row, bus width settings), it should work.

uboot/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:
uboot-imx.git - Freescale i.MX u-boot Tree 

2. please try baremetal sdk test with jtag (..src/tests/ddr_test.c), perform read/write some memory location,

check signals with oscilloscope

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Best regards
igor

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riteshpatel
Contributor II

Hi Igor,

Thank you very much for the extended support.

We found that NVCC_LVDS supply was not connected to power rail & NVCC_LVDS gives power to the DDR IO drivers.

Now we are getting the proper signal on Reset, CKE & Clock lines.

We also run DDR calibration on DDR test utility successfully. 

However, we are not getting u-boot prompt. Looks like now there is some issue in the u-boot (or may be DCD issue). 

1) We have checked the UART port configuration in u-boot. What are the other changes required to get the prompt?

2) We have found that there is SoC silicon revision number change, what are the patches we need to apply for this? (We are using Nitrogen6x which is having 1.2 however our custom board has 1.3)

3) We are using attached .cfg file which is generated from attached excel.

Thanks,

Ritesh.

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riteshpatel
Contributor II

Hi Igor,

Thank you very much for your quick support.

We got U-boot prompt on UART console after changing the UART pin muxing.

Regards,

Ritesh.

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riteshpatel
Contributor II

Hi Igor,

 

Please check attached logs for below two tests.

1) We have checked "stress test"  we are getting error as attached in the logs.

2) We have checked by writing single DDR memory 0x10000000 with 0x50505050 and read back the same, it is giving same results. 

We do have certain questions for DDR related modifications

1) As you suggested the "DQS errors" to be no fatal at the bring-up time, we have started configuring the DCDs in the u-boot and we are using following configuration settings for our "MT41K256M16TW-107" DDR.

(NOTE: We have taken reference of below settings from 2x256mx16.cfg and modified the MDASP and MDCTL registers.)

Can you please confirm whether the done settings are correct or not and let us know the modification required ?

====================================================================

DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
DATA 4, MX6_MMDC_P0_MDCTL, 0x84180000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006

====================================================================

2) We have also tried to use the same settings given by above excel and generated the .cfg file, however it was not working and board flashing is failing. 

3) Is there any other modifications required in the u-boot code to get the u-boot code? 

4) From the layout front we have checked the checklist that you have provided.

5) For flashing of the devices, we are using imx_usb binary, the flashing is successful however there is no activity on serial console. Debugging further we found that with the "imx_usb -d -v" option, the verification of the DDR written data is getting failed due to which there no console prints on serial and for this we are assuming that there is some issues with u-boot or DCD configurations for DDR. Can you please let us know what may go wrong in the above configuration file ?

Greatly appreciate your earliest response

Thanks,

Ritesh.

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