DDR3 - What are good delay windows?

[tkl]

Hi,

after using the DDR Stress Tester to get calibration values for DDR3 according to "Freescale i.MX6 Port Application Guide - DDR3" I am wondering how to judge the resulting delay windows. In the document it says on freescale evaluation boards the window for DQS gating is 1.1 to 1.2 tCK and for read write delay it is 0.3 to 0 4 tCK. So this are good, acceptable values? I have nothing to compare it to. What windows are you getting on your designs?

[igorpadykov]

Hi Torben

yes these margin values which gives MX6 DRAM Port Application Guide-DDR3

on p.14,17 are good and recommended

Freescale i.MX6 DRAM Port Application Guide-DDR3 

Best regards
igor
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