DDR stressTest imx8mp LPDDR4

[Cyriactoms]

I am running a ddr test for imx8mp lpddr4

I am using   MT53E1G32D2FW-046 WT:A   lpddr4/sdram  

For running the ddr tool i have created .ds file will attach the file here 

While downloading the script for calibration its showing like

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 4096MB
Density per controller is: 8192MB
Total density detected on the board is: 8192MB
============================================

Please re-download with the correct value

i am not able to calibrate. Is the issue regarding the imx8mplpddr4 spreadsheet or any other issues. 

[Cyriactoms]

In the ddr controller spreadsheet i have given the value 

Density per channel per chip select (Gb)1:	8
Number of Channels	2
Number of Chip Selects used2	2
Total DRAM density (Gb)	32

when running the stress test the out put showing 

DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 4096MB
Density per controller is: 8192MB
Total density detected on the board is: 8192MB

which is not same as in the spreadsheet

[JorgeCas]

Hello,

Could you please try with DDR Tool for i.MX?

Also, please share your RPA file.

Best regards.

[Cyriactoms]

i am trying with ddr tool for imx and getting this output

[Cyriactoms]

DDR configuration DDR type is LPDDR4 Data width: 32, bank num: 8 Row size: 17, col size: 10 One chip select is used Number of DDR controllers used on the SoC: 1 Density per chip select: 4096MB Density per controller is: 4096MB Total density detected on the board is: 4096MB ============================================ MX8M-plus: Cortex-A53 is found ************************************************************************* ============ Step 1: DDRPHY Training... ============ ---DDR 1D-Training @1600Mhz... my calibration is not happening its getting stuck

[Cyriactoms]

INFO test_app [INFO]: Execute Training Firmware for 1D pstate0@1300MHz...
INFO test_app [INFO]: Training Firmware completed for 1D pstate0@1300MHz with status 3; Execution ended in 0s.5ms.842us...
INFO memtool.common.base_test Read phy status DDR PHY: 1D training failed
INFO root Number of logged items 0x3
ERROR memtool.common.base_test DDR PHY: 1D training failed

[JorgeCas]

Hello,

Got it, thank you for the information.

Please share the entire log with first configuration and your LPDDR4 schematic section.

Best regards.

[Cyriactoms]

It was a hardware issue it got resolved thank you

[lxhan92]

Hello, may I know the root cause of that? I have the same issue when trying to train LPDDR4 the first time.