DDR differential clock termination design rules

[ko-hey]

Hi all

I have a question about differential clock termination design rules.

According to the DDR section of schematics tab in following Check List,  user have to check Micron's Technical Note.

https://community.freescale.com/docs/DOC-93819

I have a question about it.

I think that user need to check only "DDR Devices's Clock Signals" section P12 and P13.

Is it correct ?

Ko-hey

[igorpadykov]

Hi Ko-hey

right, user needs to check "DDR Devices's Clock Signals" section P12 and P13.

Note that this app note is given as additional recommendation, so FSL documents

HW Design Checking List for i.Mx6DQSDL and IMX6DQ6SDLHDG

supersede any recommendations in that document.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------