DDR-SDRAM board pattern.

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DDR-SDRAM board pattern.

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takashitakahash
Contributor III

Hi community.

Our customer has question below.

I have a question about the circuit board wiring pattern of DDR3-SDRAM to IMX6SLX.

In this our board, we have to consider the application of the Fly-by Topology wiring.

For wiring length spec of SDCLK, description of "IMX6SXHDG" of "Page33 Table 3-3" In Max.2.25 [inch], on the other hand: In the wiring example of "Page48 Table 3-6" is  2779.48 [mil] .

It  looks like does not meet the provisions.

Are you sure  do I think this is in any way?

Whitc is correct?

[Note]

Although we started the board design in our company, it is currently difficult situation to meet the Max.2.25 [inch]. If possible, I want to relieve this spec.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,


Basically, the best approach - to use simulation technique for PCB design. In the same time, general rules may be provided for customers to simplify their PCB considerations, but note, for assurance such rules are very strong. So, if it is possible simulate the PCB design please use it, if cannot - please follow general (and more strong) recommendations, such as provided in the Design Guide (IMX6SXHDG).

  The reference design may not meet all PCB design requirements, since  it was implemented earlier. 

Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

Hello,


Basically, the best approach - to use simulation technique for PCB design. In the same time, general rules may be provided for customers to simplify their PCB considerations, but note, for assurance such rules are very strong. So, if it is possible simulate the PCB design please use it, if cannot - please follow general (and more strong) recommendations, such as provided in the Design Guide (IMX6SXHDG).

  The reference design may not meet all PCB design requirements, since  it was implemented earlier. 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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takashitakahash
Contributor III

Hi Yuri.

thank you for your answer.

We advances your replied as follows using the Simulation.

So, please tell me IMX6SX (MMDC) of acceptable skew value  on SDCLK and DQS.

Write Leveling / Read Leveling maximum Skew value can be adjusted please inform me.

Thanks,

Best.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

the following appnote helps to clarify the issue.

http://www.nxp.com/files/32bit/doc/app_note/AN4467.pdf

Regards,

Yuri.

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