DDR Memory Map default config value for TZASC

[myungjinhwang]

Dear NXP team.

I have a question about DDR Memory Map default config.

I got the answer from the bellow link.

DDR Memory Map default config value for TZASC

But

the OCOPT_CFG valuses are :  

- OCOTP_CFG3 : 0x00620302

bit	23	22	21	20	19	18	17	16
values	0	1	1	0	0	0	1	0

then i think DDR Memmory Map default config bit[21:20] is 10(4kb interleaving Enabled).

but i got an answer from nxp team. it's Single DDR channel...

could you let me know why?

Best regards,

MyungJin Hwang

[myungjinhwang]

Hello Yuri.

Thanks for the reply...

then one more question.

How to find or know that BOOT_CFG[3] relates to OCOTP_CFG4?

is there some table info?

Have a great day,

MyungJin Hwang

[Yuri]

Hello,

To be oriented how register OCOTP_CFGx correspond to the fuses ,

please use column “Addr” in tables of Chapter 5 (Fusemap) and

column “Absolute address (hex)” in table in section 46.5 (OCOTP Memory
Map/Register Definition) of the i.MX6 D/Q RM.
  For example, value of OTP Bank0 Word0 (Lock controls) (OCOTP_LOCK)

at 0x021B_C400 corresponds to Table 5-2. (Lock Fuses) with 0x400 offset.

Regards,

Yuri.

[Yuri]

Hello,

  The BOOT_CFG[3] relates to OTP Bank 0, word 5 : that is, bits 23-16 of

OCOTP_CFG4 should be used. 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------