DDR Controller Configuration Spreadsheet for using just one DDR controller

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DDR Controller Configuration Spreadsheet for using just one DDR controller

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nredi
Contributor I

I'm trying to configure the DRAM chip with my custom board based on i.MX8QM processor.

DMRAM chip is an LPDDR4 Micron MT53B512M32D2NP-062.

The SCU FW version is 1.2.8 and I attached the platform/board/<my_board>/board.c file.

I also attach the Device Information table in the Register Configuration worksheet tab and the correspondant DCD CFG automatically generated file.

In this configuration everything works fine, here is the log taken from the consolle during boot.

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:

board_ddr_config OK

 

LP4_MANUAL_DERATE_WORKAROUND

--> OK

DDR frequency = 1596000000
board_system_config(0, 0)
Changing WDOG Action For WDOG ----> SUCCESS !

Configuration DONE
Start PMIC init
Finished PMIC init

board_init(5)
board_init(2)
SECO ---> Enabling LDO3 8 @ 1.8V
SECO ---> Enabling LDO3 9 @ 2.5V
ROM boot time = 177342 usec
SCFW boot time = 63344 usec
Banner = 20118 usec
Init = 2751 usec
Config = 8238 usec
DDR = 14688 usec
SConfig = 8569 usec
Prep = 5160 usec

*** Debug Monitor ***

Following this guide, I'm trying to configure the DRAM to make it just use one DDR controller instead of both (so just DRC_0 controller in use). I modify the value of the cell "Total number of DDR Controllers in use. Note: if selecting "1" then only DRC_0 will be used." changing it from 2 to 1, but at boot I got the SCU FW code stucked in a loop. It seems to fail executing the line 720:

err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT);

Here is the log.

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:


Hello from ricciolino!

 

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:


Hello from ricciolino!

 

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:


Hello from ricciolino!

 

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:


Hello from ricciolino!

 

Hello from SCU (Build 3372, Commit bcea244d, Nov 04 2019 02:00:57, Built on Thu Dec 9 15:54:08 2021)

SCFW build for C54-D09

DDR: MT53B512M32D2NP_062
DCD: MX8QM_B0_LPDDR4_RPA_1.6GHz_v19_MT53B512M32D2NP_062_DCD_CBT

board_init(0)
board_init(1)
SECO ---> Enabling CLK 32K on GPIO0_07
board_init(4)
board_init_ddr(0)
SCFW:
...

... and so on...

Any suggestions to solve this problem?

Thanks.

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