DDR Calibration

[developer123]

I'm using a SOM manufacturer's product that includes the i.MX6.

I’ve noticed that the DDR3 calibration results on the actual hardware differ from those obtained using the DDR Stress Test Tool. Specifically, the tool appears to use the median value for DQS gating, whereas the actual device calibration seems slightly offset from the center.

I’m wondering if this discrepancy is due to the adjustment described in the following document:

AN4467_Rev2.pdf
Section 12.3.2 "Calibration Sequence Setup with Predefined Data Content" states:
— Read the HW_DG_UPx value from MMDC0/1_MPDGHWSTx
— Subtract 0xC0 (3/4 cycle)
— Write the 7 LSBs of the result to MMDC0/1_MPDGCTRLx[DG_DL_ABS_OFFSETx]
— Write the 4 MSBs of the result to MMDC0/1_MPDGCTRLx[DG_HC_DELx]

Or could there be another reason why the calibration results differ?

Thank you for your assistance.

[pengyong_zhang]

Hi @developer123 

Could you explain more about you mentioned calibration results on the actual hardware? The DDR calibration use the firmware, It is a behavioral adjustment of the software. The two will not conflict.

B.R