Hi Josh
seems changes in CCM Clock Output Source Register changed
bit8 CLK_OUT_SEL in register CCM_CCOSR described in
sect.18.6.21 CCM Clock Output Source Register (CCM_CCOSR)
i.MX6DQ Reference Manual (rev.4 9/2017)
http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
So frequency can be adjusted to previous value using bsp sources for example
in boundary devices releases where supported sgtl5000:
uboot/board/boundary/nitrogen6x/nitrogen6x.c
In general for emissions one can try to tweak drive strength pads
which produce that signal, like GPIO_0 [ALT0 CCM_CLKO1], CSI0_MCLK [ALT3 CCM_CLKO1]
and others.
Best regards
igor
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