Concurrent DDR writes from SDMA and AP Core

[rolfw]

Hi

how are concurrent writes from SDMA FU Bursts and writes from A9 Core to non-cached memory  are arbitrated? Is it possible to give SDMA writes prio over A9 Core writes?

Thanks

Rolf

[rolfw]

Perfect! 

Great thanks!

Rolf

[igorpadykov · Accepted solution]

Hi Rolf

arbitration is handled by nic-301 (its documentation can be found on arm.com)

please check Chapter 45 Network Interconnect Bus System (NIC-301) i.MX6DQ Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

Best regards
igor
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