Hi,
We've been working with an IMX334 image sensor on the dart-mx8m development kit. We are trying to capture a 4K@30 fps streaming. We configure the image sensor to use 4 lanes (891 Mbps/lane) and RAW10 but so far we only get distorted images (see images below). Frame rate is not correct either.
We've already validated that is possible to capture RAW10 images with two other sensors, the OV5640 and the AR0144 (750 Mbps/lane).
From these tests, we have observed that the main difference of the IMX334 with respect to the other sensors already validated, is the data rate and the number of CSI-2 lanes.
In the iMX8M documentation ("i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual") one can find the following information about the MIPI Host Controller:
- clk: RX Controller Core Clock input. This
clock must be exactly equal to or faster
than the receive byteclock,
RxByteClkHS_ln0, from the RX DPHY.- clk_ui: ser interface clock. The frequency of
clk_ui must be such that the data
received on the data_out output is
greater than or equal to the total
bandwidth of the physical MIPI interface.
Clk_ui has no relationship requirement
with regards to ‘clk’ other than the
bandwidth requirement mentioned
previously.- esc_clk: Rx Escape Clock. This must be the
same escape clock that the RX DPHY
receives.As an example, if RGB888 data is being received, the
user interface data width will be 24 bits wide (1 pixel per clk_ui rising edge and each
pixel is 24 bits). As an example, let the MIPI interface run at 1000Mbps with a single
lane. The data rate into the CSI-2 RX controller will be 125MBps so clk must run at
125MHz or higher. Since the user interface is 3 bytes wide, clk_ui must run at 125MHz/3
or higher to keep up with the incoming data.
Based on this, I assume clk must be >= byte rate and clk_ui must be >= pixel rate.
In our case, we have 891Mbps/lane which gives us: 445.4 MB/s and 356.4 MP/s so I'm assuming one should be clk and the other one clk_ui.
From the driver perspective, we have access to 3 clocks that are called: CORE, PHY and ESC. There is no
documentation about the relationship between the clk/ckl_ui in RM and CORE/PHY in driver but my guess is
that clk is what in the device tree is called CORE clock and clk_ui is what is called PHY. Based on this I tried changing the values of CORE and PHY clocks in iMX8 to values greater than the ones in my calculations but I have had no luck. With different clock values, I can see how the capture framerate changes but the captured data is never right.
Also, the documentation says that the clocks have to be exactly equal or greater than a certain value but in
practice this doesn't seem to be true as if I set the clocks too high, the capture stops working at all so it
looks like we have to use a value close to the actual capture data rate but the problem is we have no way of
generating the exact values of the calculations. If we have, for instance, a source clock of 1000MHz for CORE and
PHY clock, we can only get 1000, 500, 333, 250, 200, ... MHz clocks (we can only divide the clock by integer numbers).
So the questions would be:
*What is the relation between clk and clk_ui with the properties CORE/PHY in the device tree (arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi)?
*How to set clk, clk_ui, esc_clk properly, how it is related to what the image sensor outputs?
Thank you in advance for your answers!
--
Jafet Chaves
Embedded Software Engineer
RidgeRun | https://www.ridgerun.com/
Hello ye,
Please check the table from 8M RM for relation between clk and clk_ui with the properties CORE/PHY.
B.R,
Hi Jafet,
I also confused about the i.MX8MQ MIPI CSI clock configuration.
But I don't think "clk_ui is what is called PHY" as you said.
Just see this clock block diagram in i.MX8MQ RM P4994.
Felix
