Hi @fazle_nabi ,
Your design is OK, I checked no problem.
The measured time of 50.2ms between SYS_nRST and VDD_1V8 supply is acceptable for your implementation. With i.MX8MP processors, the voltage application sequence itself is more important than the exact timing between steps. Most minimum voltage ramp-up timing values in the documentation are 0ms, indicating that specific delays are not strictly required as long as the proper sequence is maintained.
The PCA9450CHN is specifically designed to work with i.MX8 processors and handles the proper power sequencing automatically. Your oscilloscope measurement showing the correct voltage sequence confirms that your implementation should function properly despite any timing differences from reference diagrams.
Hope this can do help for you
Wish you have a nice day
Best Regards
Rita