Clarification on Power-Up Sequence Timing Between SYS_nRST and 1.8V Supply for i.MX8 + PCA9450CHN

[fazle_nabi]

Hi NXP Team,

We are using an i.MX8 processor with the PCA9450CHN as the PMIC for the processor’s power supply. We could not find the specified power-up sequence timing between SYS_nRST and the PMIC's supply VDD_1V8 ( Output of BUCK5FB) in the datasheets for either the processor or the PMIC.

Could you please help us with the correct timing requirements or specifications for the power-up sequence between SYS_nRST and the VDD_1V8 supply?

We have measured the power-up sequence time between SYS_nRST and the VDD_1V8 supply—please refer to the attached image. Could you please confirm whether the measured time (50.2 ms) is correct?

Thank you for your support.

Regards
Fazle Nabi 

[Rita_Wang]

Hi @fazle_nabi ，

I run the linux 5.4.70 version on board, when board power up the timming is about 30ms, you can refer to :

Wish you have a nice day

Best Regards

Rita

[fazle_nabi]

Hi @Rita_Wang Thanks for your quick Reply,

I wanted to know the acceptance criteria for the power-up time of the VDD_1V8 and SYS_nRTS signals. We’re unable to find the acceptable range in any of the datasheets, either for the processor or the PMIC.

We measured the power-up time between VDD_1V8 and SYS_nRTS and obtained approximately 51 ms with kernel version 5.4.70. Please refer to the attached image for reference.

Thanks for your quick support.

Regards
Fazle Nabi

[Rita_Wang]

Hi @fazle_nabi ,

Your design is OK, I checked no problem.

The measured time of 50.2ms between SYS_nRST and VDD_1V8 supply is acceptable for your implementation. With i.MX8MP processors, the voltage application sequence itself is more important than the exact timing between steps. Most minimum voltage ramp-up timing values in the documentation are 0ms, indicating that specific delays are not strictly required as long as the proper sequence is maintained.

The PCA9450CHN is specifically designed to work with i.MX8 processors and handles the proper power sequencing automatically. Your oscilloscope measurement showing the correct voltage sequence confirms that your implementation should function properly despite any timing differences from reference diagrams.

Hope this can do help for you

Wish you have a nice day

Best Regards

Rita

[Rita_Wang]

Hi @fazle_nabi ,

How about the design? The same with our reference board?

Wish you have a nice day

Best Regards

Rita

[fazle_nabi]

Yes,  Please refer the PIMIC schematic.

Thanks!

Regards

Fazle

[fazle_nabi]

Please refer the attached PIMIC Schematic design.

Thanks!

[fazle_nabi]

Hi @Rita_Wang Please Refer the Attached Image 

Thanks!

[Rita_Wang]

Hi @fazle_nabi ,

Due to training all last week, and sorry miss your thread. I have confirmed that we do not have the data, I will measure our board and then share you the result.

Wish you have a nice day

Best Regards

Rita