Hi @jeanpihet,
In the i.MX Porting Guide (UG10165), section 3.2.1 explains how DDR init varies by SoC family. “Point 6” there says that i.MX8M parts rely on U‑Boot SPL to initialize DDR (not DCD), and that users must modify the SPL DDR PHY/controller code. That statement is about 8M devices specifically.
For i.MX8ULP, the boot flow is similar to 8M in that DDR is initialized by U‑Boot SPL, not by a DCD table in U‑Boot proper. The flash.bin built by imx‑mkimage contains two AHAB container sets:
a first set that the ROM loads to OCRAM (SPL + uPower + ELE firmware), and a second set (U‑Boot proper + TF‑A) that SPL loads to DDR after SPL has initialized DDR.
Practically, this means you customize/tune DDR in the SPL code for i.MX8ULP (just as with 8M), not in a DCD inside U‑Boot proper.
Does U‑Boot SPL for 8ULP already provide DDR init? If not, where do I update it?
Yes. For 8ULP, the SPL path is responsible for bringing up DDR. You’ll find the DDR init hooks under the SPL portions of the NXP U‑Boot tree for your board/SOC (board directory + arch/arm/mach-imx/… + 8ULP-specific DDR PHY/controller glue). That SPL then loads the second container (TF‑A + U‑Boot proper) into the freshly initialized DDR
Booting & flashing over USB (UUU) is it supported? Which images can I boot?
Yes, UUU (Universal Update Utility) over USB is supported for i.MX8/8ULP via the Serial Download Protocol in ROM. You can load a flash.bin directly to RAM and boot it, or use a .uuu script to perform more complex sequences.
Is your build procedure correct?
For 8ULP you do need u-boot-spl.bin, u-boot.bin (U‑Boot proper), bl31.bin (TF‑A), upower.bin, and ELE firmware (named mx8ulpa2-ahab-container.img for A2 silicon) placed in imx-mkimage/iMX8ULP/ before running make.
So, yes — your overall steps are right for 8ULP. The only thing to double‑check is which imx‑mkimage target matches your boot type (single‑boot vs dual‑boot) and destination (RAM vs FlexSPI vs eMMC) for your bring‑up stage.