Can i.MX8M mini use DDR3?

[danny_kim]

Hi 

I purchased i.MX8M mini EVK
The EVK I purchased has 2GB of LPDDR4 designed.
(There are also EVKs designed with DDR4)

Can I change to  DDR3?
Can I design with 512MB or 1GB?

The product I am designing now does not have much work on the video side.
It is about checking the video seamlessly by connecting HD-class CAM with USB.

Please review
Thank you

[mrudangshelat1]

Hi Danny,

i.MX8 Mini supports 32/16-bit LPDDR4 (up to 1.5 GHz), DDR4-2400, and DDR3L-1600. It also supports up to 8 Gbyte DDR memory space.

Regards,

Mrudang

[danny_kim]

Hi Mrudang

DDRL can be used. Can I modify it by referring to the DDR4 design?
Please share any information I can refer to.

And is there no problem with 1GB or 512MB other than 2GB?

Thank you

[mrudangshelat1]

Hi Danny,

Yes DDR3L can be used. And there is no issue with 1GB or 512MB.

Kindly share your schematic once you are done with the interfacing.

Mrudang

[danny_kim]

Hi Mrudang

I designed schematic a part of i.MX8, DDR3L, eMMC

Please review my schematic

Thank you

[mrudangshelat1]

Hi Danny,

Please refer to IMX8MMHDG: i.MX 8M Mini Hardware Developer’s Guide for DDR3L.

• Refer complete sec 3.4 DDR design recommendations for pin signal assignment, signal swapping etc.
• Also, refer to reference schematic pg. no 5 of SCH-35104 for DDR3L interface and net swapping based on signal routing.
• eMMC interface looks good. (Reference pg. no 9 of SCH-31399 C2)

Regards,

Mrudang

[danny_kim]

Hi Mrudang

I will refer to IMX8MMHDG: i.MX 8M Mini Hardware Developer’s Guide

But I have a question
Where is the circuit diagram for reference (SCH-35104, SCH-31399)?
This is not in IMX8MMHDG: i.MX 8M Mini Hardware Developer’s Guide, what document?
Is the document I know different from the document you are telling me?
Please let me know

Thank you

[mrudangshelat1]

Hi Danny,

Please find the attached schematic for your reference.

Regards,

Mrudang

[danny_kim]

Hi Mrudang

The attached file is a circuit diagram for LPDDR4 and DDR4
Is there any circuit diagram for DDR3L?

[mrudangshelat1]

Hi Danny,

The schematic is based on DDR4 and LPDDR4. but they have also mentioned DDR3 as well. It means this reference schematic is also applicable for DDR3 signal interface as well.

Section 3.4 of  IMX8MMHDG: i.MX 8M Mini Hardware Developer’s Guide has provided pin signal assignment for all 3 DRAM.

Mrudang

[danny_kim]

Hi Mrudang

I referred to the document composed of DDR4 (SPF-35104) and prepared a circuit diagram for review. (The circuit diagram was attached)
Have you seen the circuit diagram I attached?
If you have seen it, please give me a comment on it

According to the document (IMX8MMHDG: i.MX 8M Mini Hardware Developer's Guide), when using DDR3L, it seems to use four DDR3L.
However, the circuit diagram using DDR4 uses two DDR4.
If there is a circuit diagram composed of DDR3L, please attach it.
Thanks

[mrudangshelat1]

Hi Danny,

Please resend me the updated schematic.

If they have used 4 DRAM for their application. If we need to use 2 DRAM based on data lines and memory density we need to connect the DQ signals and address signals.

Mrudang.

[danny_kim]

Hi Mrudang

Among the above ripples, there is a circuit diagram I attached
I want you to give me a comment on it

1. Only two DDR3Ls are used? Should I use 4?
2. Please inform the wrong part of the attached circuit diagram.
3. Please attach a reference circuit diagram written in DDR3L.
4. Is there a circuit diagram written in i.MX8MM and DDR3L?

Thank you

[mrudangshelat1]

Hi Danny,

The attachment is missing.

Please share the updated one.

What do you mean by the wrong part?

Do you use Skype?

Share your id.

Mrudang

[danny_kim]

Hi Mrudang

Attached file is here

'Wrong part' is to review the circuit diagram
I'm sorry, but I don't use Skype
Is there no DDR3L circuit diagram?

Thank you

[mrudangshelat1]

Hi Danny,

As I have informed you earlier, pls assign the data lines as shown in ref design.

Please update.

Mrudang

[danny_kim]

Hi Mrudang

I modified the data line and attached circuit
Is there anything else that could be a big problem besides the data line?

I think the wiring of DDR4 and DDR3L is similar, so I can do artwork by referring to the DDR4 schematic and PCB file.

Thank you

[mrudangshelat1]

HI Danny,

Now DRAM looks good. I believe Parity, Ten and ACT_n pins are not there in DDR3L. Those are for DDR4.

Is there anything else that could be a big problem besides the data line?

Ans: Data Mask, Data strobe has to be matched with Data lines. Earlier schematic it was not matching.

I think the wiring of DDR4 and DDR3L is similar, so I can do artwork by referring to the DDR4 schematic and PCB file.

Ans: Yes.

Mrudang

[danny_kim]

Hi Mrudang

I don't use it in DDR3L, but I will treat Parity, Ten and ACT-N as TP

The other part of the wiring of DDR3L is said to be okay, so I will start working as it is.
Thank you

[mrudangshelat1]

Sure

[danny_kim]

Hi Mrudang

i.MX8M mini is applicable to DDR3L and 512MB is also available.
Then I will design DDR3L, 1GB
I'll share it when finished, so please review
Thank you