As I understand it the LVDS channels can use one of 5 clocks,
000 pll5 clock
001 pll2 352M PFD
010 pll2 396M PFD
011 MMDC_CH1 clock
100 pll3_sw_clk
and it can also have a post 3.5/7 divider on that clock.
We use pll5 as our IPU DI clock parent. We further use CHSCCDR and CSCDR2 to divide the clock some more to drive the DI.
Is there a way to reuse that same clock the DI is using as the LVDS clock? I can't seem to see that anywhere in the reference manual. For example the parallel RGB is fine in this case because it uses the output DI clock. I would have thought that there would be a path to feed that output DI clock into LVDS.
Is this possible? Is there something I am missing?
