CSI transfer rates and limitations

[dennis3]

Hello,

I'm working with a custom camera on an imx8mq board.  I see in the specs for the imx8 that we can do 1080p@30 which is working fine for me.  Other sensors on evaluation boards for the imx8 that I've looked at that go to 4k must go down to 15 fps.  I'd like to more understand where the limitation is.  

I understand from other posts that the mipi-phy could support 4k@30 data rates but that the imx8 can't support it.  I'd like to better understand which component has the limitation and what it's capabilities are so that I can support some resolution larger than 1080p but still maintain 30fps.  I don't need to get all the way to 4k.

If someone can shed light on where to find the pipeline specs that better describe this process I'd much appreciate it.

[joanxie]

if you mean imx8mq mipi csi, refer to the reference manual:

Two MIPI-CSI2 Display Interfaces:
• Each MIPI-CSI2 is 4 channels supporting one camera input. Supports 5M pixel
at 15 fps, 1080p30, 720p60, VGA at 60 fps
• Maximum bit rate of 1.5 Gbps

[dennis3]

Thank you for the reply.  Just to clarify, I've found the 1.5Gbps spec but it wasn't clear if that is the combined bitrate or a per lane bitrate.

5M at 15fps is around 1.2 Gbps (yuv422) so that suggests it's a limit on the combined bitrate not each lane?  Is that right?

[joanxie]

yes, you are right, 1.5Gbps is for each lane

[dennis3]

I realize each lane can achieve 1.5Gbps.  However if all lanes are operating at 1.5Gbps, the combined total of 6Gbps is not supported I understand.  I want to understand what what combined limit is supported.  Is that also 1.5Gbps?

[joanxie]

i.mx8M mipi csi max bandwidth is 1.5Gbps * 4 = 6Gbps, so can support up to 4K@30

[dennis3]

Ok, thank you for clarifying.  I also subsequently found in the RM the same statement.

I've found on this forum, a reference clock for 4 lane CSI for 1080p suggested by nxp engineers.

<266000000>, <333000000>, <66000000>

What is a suggested clock rate for 4k@30fps?  If I increase the clock rate to handle the faster rates, is there any consideration for still being compatible with smaller preview frame sizes? 

[joanxie]

if you want to capture 4k@30 from mipi csi, you need to set

  assigned-clock-rates = <266000000>, <333000000>, <66000000>, CSI core clock is from SYS1_PLL_266M

[dennis3]

Thank you joanxie Can you help me understand where my calculation is wrong in the following?

Section 13.8.3.4 of the reference manual has a clocking example.  clk must keep up w/ d-phy clock.  clk_ui must keep up with incoming data. following numbers modified from that example

1) We're in single pixel mode (data type is yuyv so 2 bytes per output pixel).  So 3264x2448 (8M) @ 30fps = ~3.8 gbps or for our 4-lane setup ~ 958 Mb/s per lane.

2) ui clock is still one pixel wide according to yuyv data type in 13.8.3.6.15

3) data rate into Rx (D-PHY) is ~958 Mb/s each lane or ~119.8 MB.

4) So since single pixel mode.. clk_ui must be same min as clk, except that there is 4 lanes.. so ~479MB/s.

By those calculations, we need a min of 479Mhz clock for clk_ui.  But that conflicts with the previous posts.  It's not clear to me clk for D-phy min requirement is for each lane or for the combined lanes, but it does seem clear that clk_ui needs to handle the combined data rate.   

* So basically, 266MHz for core clock seems OK as long as it's per lane.. which seems to be right.

* 333MHz for clk_ui seems insufficient?? 

* is 66Mhz for esc clock OK regardless of the other two clocks?  I didn't find a relationship between it and the other two in the reference manual.

I'm posting this because we still can't get it to work over 15fps for 4k video.  

[jashka]

Hello. Several years have passed, but I believe I am running into the exact same issue as you. Did you manage to resolve this issue or happen to recall any helpful information?

[sharad_yadav]

Hello, can single CSI-2 lane transfer 648x488 @30fps?? FYI: I am interfacing CVBS analog camera with i.mx8m nano over a single CSI-2 lane. Planning to use Analog devices ADV7282A-M video decoder chip for CVBS to CSI conversion. Regards, Sharad