CSI-2 i.MX6Q question. what is the register and bit I need to watch to determine when CSI-2 end of frame packets are received through the interface? Is the source code for debug "ipu_common.c" and is the "IPU_INT_STAT" the right register? Debug higher up indicates 33fps, and the data stream on the input to the CPU says 60fps. Trying to determine why I am only getting half the frames.
Thanks for you input!
In IPU_INT_STAT register, there is EOF bit, when the bit is set, means one frame video data has been received. CPU will know how many frames have been received by counting interrupt times in one second.
Thank you for the reply, I see this bit.
Do you or anyone else know if the CSI0_MCLK, CSI0_PIXCLK, or CSI0_VSYNC is needed for proper operation of the CSI input? We are providing a CSI-2 video data stream at 60fps but the iMX6 does not seem the be catching them. We see interrupts at about 30fps maximum.