CCM_CCGR116(Flexcan1) that set by M4 core in imx7d is cleared during linux boot

[hideo_yamashiro]

Dear anyone to know about this issue.

We are using a board based on mx7dsaberesd.

And we are trying to work m4core's program with flexcan1 and linux version 4.14.

But we cannot flexcan1 on m4core.

It seems that linux during its boot is clear CCM_CCGR116(flexcan1 0x30384740) .

(1).read CCMCCGR116 on u-boot after start m4core's program.

    =>md.l 30384740

    30384740: 00000003

     It's OK.

(2).read CCM_CCGR116 on linux after its boot.

      $get_regi_value 30384740 l       <---this program to read a register with mmap api.

      30384740(=30384000+00000740) => 00000000

      CCM_CCGR116 is cleard.

Could you teach us how to solve this issue?

In Addition, flexcan1 / 2 are disabled in devicetree for linux.

We do not know where source program of linux clears CCM_CCGR116.

And Also How to solve this issue.

Thanks for your help.

[igorpadykov]

Hi Hideo

one can look at similar issue on

https://community.nxp.com/t5/i-MX-Processors/i-MX7-M4-UART-change-the-speed-during-linux-booting/m-p...

and comment out "can1", "can2" in linux clk driver:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx7d.c?h=imx_4.14.78_...

Best regards
igor

[hideo_yamashiro]

Hi, igorpadykov. Thanks for your reply. I could not find imx_clk_set_parent() and imx_clk_set_rate() for flexcan1 and 2 like below. imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); You mean that the following lines are need to comment out. clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate3("can1_cg", "can1_src", base + 0xac80, 28); clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate3("can2_cg", "can2_src", base + 0xad00, 28); clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0); clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0); It seems that clks arrays should set any appropriate values. Could you tell us what values the arrays are set? Best regards, Hideo yamashiro.

[hideo_yamashiro]

Hi, igorpadykov. I repost same contents because previous post is so difficult to read. Thanks for your reply. I could not find imx_clk_set_parent() and imx_clk_set_rate() for flexcan1 and 2 like below. imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); You mean that the following lines are need to comment out. clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate3("can1_cg", "can1_src", base + 0xac80, 28); clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate3("can2_cg", "can2_src", base + 0xad00, 28); clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0); clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0); It seems that clks arrays should set any appropriate values. Could you tell us what values the arrays are set? Best regards, Hideo yamashiro.

[igorpadykov]

Hi Hideo

one can try to comment out all "can1", "can2"  entries in linux clk driver, since they are not used

in linux:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx7d.c?h=imx_4.14.78_...

Best regards
igor

[igorpadykov]

Hi Hideo

one can try to comment out all "can1", "can2"  entries in linux clk driver, since they are not used

in linux:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx7d.c?h=imx_4.14.78_...

Best regards
igor

[hideo_yamashiro · Accepted solution]

Hi, igorpadykov

Thank you for your cooperation.

I solved my issue.
I modified 2 source files like below.

[clk-imx7d.c]

clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0);

↓ modify

clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4_unused_ignore_for_m4("can1_root_clk", "can1_post_div", base + 0x4740, 0);

[clk.h]

static inline struct clk *imx_clk_gate4_unused_ignore_for_m4(const char *name, const char *parent,

void __iomem *reg, u8 shift)

{

if (imx_src_is_m4_enabled())

return clk_register_gate2(NULL, name, parent,

CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE | CLK_IGNORE_UNUSED,

reg, shift, 0x3, 0, &imx_ccm_lock, NULL);

else

return clk_register_gate2(NULL, name, parent,

CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | CLK_OPS_PARENT_ENABLE,

reg, shift, 0x3, 0, &imx_ccm_lock, NULL);

}

Thanks.