Bus isolation of iMX6SL boot configuration pins

[torus1000]

Hi community,

I'm new user of iMX6SL.
I found the difference between MX6SL-EVK and MX6DL-SaberSD boot config pins.
It seems EVK has line drivers(74LVC244APW) improved bus isolation. Please see attached.
I have questions as following. Is there anyone can help?

(Q) Is there another special reason to add line buffers for EVK?

(Q) Is it OK to eliminate line buffers for custom MX6SL board?

Thanks.

[Yuri]

  The boot pins are latched at POR rising edge, but - strictly speaking -

the hold time  is not specified. On the i.MX6 SL EVK bus isolation buffer

is applied and the next note is provided :

"i.MX6SL reads values approximately 300uS to 1mS after reset released.

Buffers are active while unit is in reset and 1ms-10ms after reset is

released."

Have a great day,
Yuri

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[torus1000]

Dear Yuri,

Thank you for quick reply. It helped me alot. Let me clarify my 2nd questions.

(Q) In terms of saving BOM cost, is it possible to remove line buffers like SabreSD did?

BR

[Yuri · Accepted solution]

  From Table 1-2 (EIM recommendations for developer’s boot modes) of

IMX6SLHDG (“Hardware Development Guide for i.MX 6SoloLite - User Guide”),
linked below :
"Isolation buffers are required because 6SoloLite pads can be set to 1.8V or 3V
logic levels while boot signals require 3V logic level to latch the boot settings.

Any pull-ups for boot configuration line must be properly isolated because there is
a chance that the system may use 1.8V logic levels".

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6SLHDG.pdf

~Yuri.