Boundary Scan test issue on IMX6UL device

[luc410]

Hi All,

I run a boundary scan test (Goepel) on a design with an IMX6UL, a PMIC MC32PF3001, a Nand Flash, a DDR3 and some other glue.
When I test Nand Flash or DDR3 and if the test time is lower than about 5s, there is no problem.
If the test time is upper than about 5s (I decrease tester clock) , when the tester release the tap JTAG (state machin is in TLR- Test Logic Reset), immediatly the IMX6 drive a low on "PMIC_ON_REQ" (pin T9), so the PMIC is turned off, then it send a low state on POR_B (pin T8) of IMX6.
Port_B is a compliant pattern, it must be high to permit the control of JTAG tap. So, it's impossible to have control of the IMX through jtag bus.
To do that, the only way is to disconnect (hardware) the main power, and wait until discharge of all capacitors.

This problem doesn't appear on INFRA test, even if the tester wait 10 mn.

Thanks for your help.

Luc Dalongeville

[luc410]

Hi Igor,

So the only way to avoid the timeout is to reprogram the IMX register but how can we do that ?

Do we have to replace the IMX on our board or can we use a tool to reprogram it ?

Thanks for your help.

Luc

[igorpadykov]

Hi Luc

it can not be reprogramed. One can attach jtag debugger

and write to register appropriate value, as for example described in AN5229

ARM DS-5 Development Studio Debug i.MX6UL-EVK.

https://www.nxp.com/docs/en/application-note/AN5229.pdf 

Best regards
igor

[igorpadykov]

Hi Luc

problem may be caused by Power-down counter described in

sect.57.5.3 Power-down counter event i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
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[luc410]

Hi Igor,

Thanks for these informations.

I have studied this paragraph in the document cited but I have not found any connection with our problem.
In fact, the component reacted as the pin ONOFF was activated: after 5 seconds, the pin "PMIC_ON_REQ" falls to 0.
Is it possible that during the boundary scan test the internal circuitry of the ON / OFF signal is activated?
Because the result we see is exactly that situation.
Note that in the design this pin is left unconnected  (logic level 1) and never activated.
This problem appear only when we use BSR register, not if we use IDCODE or BYPASS register.

Best regards,

Luc

[igorpadykov]

Hi Luc

power-down counter behaves exactly as the pin ONOFF so it has connection to observed problem.

Can issue be reproduced on NXP i.MX6UL EVK reference board.

Best regards
igor

[luc410]

Hi Igor,

Infortunatly, I have no reference board.

I am not a designer, my job is to do boundary scan test program to test  a board, and on this board there is an IMX6UL device.

So, I use JTAG TAP as define in 1149.1 rules. When the IMX stay in "extest" more than 5 s, even if we execute tapreset or not, output are controlled by logic core and not the Boundary Scan cells, so the signal "PMIC_ON_REQ" falls to 0, even when there is a 1 in the corresponding BS cells.

Is it possible to disable this timeout by boundary scan action ?
In our JTAG tools (Goepel), we can only access boundary scan register (ID_CODE, BYPASS, Instruction REGISTER,BSR).

Thanks for your help.

Luc

[igorpadykov]

Hi Luc

timeout can be disabled by bit PDE register WDOGx_WMCR,
as described in sect.57.7.5 Watchdog Miscellaneous Control Register
(WDOGx_WMCR) i.MX6UL Reference Manual, it can not
be disabled by boundary scan action.

Best regards
igor