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Bootloader can not jump to Application in IMXRT1062

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Bootloader can not jump to Application in IMXRT1062

‎02-23-2023 02:20 AM
591 次查看
xuanthodo
Contributor I

Hi everyone,

I'm using Teensy4.1 Board. It use main MCU IMXRT1062 and external flash Winbond W25Q64jVXGIM 8Mb.
I have a issues about jumping to Application from Bootloader. The application address is 0x60030200.
I can't jump to application from bootloader. But when I clone the bootloader and make it to an application by changing address offset. I jump it successfully.

Some details below:

- LinkerScript: I change the Application Addr to 0x60030200. 

+ In bootloader:

/*
 * GENERATED FILE - DO NOT EDIT
 * Copyright (c) 2008-2013 Code Red Technologies Ltd,
 * Copyright 2015, 2018-2019 NXP
 * (c) NXP Semiconductors 2013-2022
 * Generated linker script file for MIMXRT1062xxxxA
 * Created from linkscript.ldt by FMCreateLinkLibraries
 * Using Freemarker v2.3.30
 * MCUXpresso IDE v11.6.1 [Build 8255] [2022-10-03] on Dec 2, 2022, 9:01:13 AM
 */


GROUP (
  "libcr_nohost_nf.a"
  "libcr_c.a"
  "libcr_eabihelpers.a"
  "libgcc.a"
)


MEMORY
{
  /* Define each memory region */
   BOOT_HEADER (r)      : ORIGIN = 0x60000000,  LENGTH = 0x2000      /* IMX Flash Configuration */
   ISR_TABLE (r)        : ORIGIN = 0x60002000,  LENGTH = 0x400       /* Max 256 interrupts on ARM processors */
   FW_VERSION (r)       : ORIGIN = 0x60002400,  LENGTH = 8
   COMMIT_VERSION (r)   : ORIGIN = 0x60002408,  LENGTH = 16
   BOARD_VERSION (r)    : ORIGIN = 0x60002418,  LENGTH = 16

   ROM (rx)             : ORIGIN = 0x60002428,  LENGTH = 0x2DBD8 /* 192K without space for versions and ISR table */

   SRAM_DTC (rwx)       : ORIGIN = 0x20000000,  LENGTH = 0x20000 /* 128K bytes (alias RAM) */  
   SRAM_ITC (rwx)       : ORIGIN = 0x0,         LENGTH = 0x20000 /* 128K bytes (alias RAM2) */  
   SRAM_OC (rwx)        : ORIGIN = 0x20200000,  LENGTH = 0xc0000 /* 768K bytes (alias RAM3) */  
   BOARD_SDRAM (rwx)    : ORIGIN = 0x80000000,  LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */  
   NCACHE_REGION (rwx)  : ORIGIN = 0x81e00000,  LENGTH = 0x200000 /* 2M bytes (alias RAM5) */  
}

ENTRY(ResetISR)

/* Define heap and stack sizes */
_StackSize = 0x1000;
_HeapSize = 0x1000;

SECTIONS
{
   /* Image Vector Table and Boot Data for booting from external flash */
    .boot_header : ALIGN(4)
    {
        FILL(0xff)
        __boot_hdr_start__ = ABSOLUTE(.) ;
        KEEP(*(.flashconfig))
        . = 0x1000 ;
        KEEP(*(.ivt))
        . = 0x1020 ;
        KEEP(*(.bootdata))
        __boot_hdr_end__ = ABSOLUTE(.) ;
    } >BOOT_HEADER

    /* Interrupt vector */
    .isr_vector : ALIGN(8)
    {
        FILL(0xFF)

        KEEP(*(.isr_vector))
    } >ISR_TABLE

    /* Version information */
    .fversion : ALIGN(4)
    {
        KEEP(*(.fversion))
        KEEP(*(.fversion*))
    } >FW_VERSION

    .cversion : ALIGN(4)
    {
        KEEP(*(.cversion))
        KEEP(*(.cversion*))
    } >COMMIT_VERSION

    .brdversion : ALIGN(4)
    {
        FILL(0xFF)
        g_STARTUP_boardversion = .;
        *(.brdversion)
        *(.brdversion*)
    } >BOARD_VERSION

    /* Section Table */
    .section_tables : ALIGN(4)
    {
         FILL(0xFF)
        /* Global Section Table */
        . = ALIGN(4) ;
        __section_table_start = .;
        __text_section_table = .;
        LONG(LOADADDR(.text));
        LONG(    ADDR(.text));
        LONG(  SIZEOF(.text));
        __text_section_table_end = .;
        __data_section_table = .;
        LONG(LOADADDR(.data));
        LONG(    ADDR(.data));
        LONG(  SIZEOF(.data));
        LONG(LOADADDR(.data_RAM2));
        LONG(    ADDR(.data_RAM2));
        LONG(  SIZEOF(.data_RAM2));
        LONG(LOADADDR(.data_RAM3));
        LONG(    ADDR(.data_RAM3));
        LONG(  SIZEOF(.data_RAM3));
        LONG(LOADADDR(.data_RAM4));
        LONG(    ADDR(.data_RAM4));
        LONG(  SIZEOF(.data_RAM4));
        LONG(LOADADDR(.data_RAM5));
        LONG(    ADDR(.data_RAM5));
        LONG(  SIZEOF(.data_RAM5));
        __data_section_table_end = .;
        __bss_section_table = .;
        LONG(    ADDR(.bss));
        LONG(  SIZEOF(.bss));
        LONG(    ADDR(.bss_RAM2));
        LONG(  SIZEOF(.bss_RAM2));
        LONG(    ADDR(.bss_RAM3));
        LONG(  SIZEOF(.bss_RAM3));
        LONG(    ADDR(.bss_RAM4));
        LONG(  SIZEOF(.bss_RAM4));
        LONG(    ADDR(.bss_RAM5));
        LONG(  SIZEOF(.bss_RAM5));
        __bss_section_table_end = .;
        __section_table_end = . ;
        /* End of Global Section Table */
       . = ALIGN(4);
    } > ROM

   /* Startup code, that won't be copied to RAM */
    .startup : ALIGN(8)
    {
        *(.startup)
    } > ROM

   /*
   * for exception handling/unwind - some Newlib functions (in common
   * with C++ and STDC++) use this.
   */
    .ARM.extab : ALIGN(4)
    {
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } > ROM

    .ARM.exidx : ALIGN(4)
    {
        __exidx_start = .;
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
        __exidx_end = .;
    } > ROM
    
   /* Vector table in RAM */
    .vectorsram : ALIGN(8)
    {
        FILL(0xFF)
        *(.vectorsram)
    } > SRAM_DTC AT > ROM

   /* Program code and other data into RAM */
     .text : ALIGN(8)
     {
         *(.csf)
         *(.text*)
         *(.rodata .rodata.* .constdata .constdata.*)
         *(.init* .fini*)
         . = ALIGN(8);
     } > SRAM_ITC AT> ROM
        
    /* DATA section for SRAM_ITC */
    .data_RAM2 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM2 = .) ;
        PROVIDE(__start_data_SRAM_ITC = .) ;
        *(.ramfunc.$RAM2)
        *(.ramfunc.$SRAM_ITC)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM2 = .) ;
        PROVIDE(__end_data_SRAM_ITC = .) ;
     } > SRAM_ITC AT>ROM

    /* DATA section for SRAM_OC */

    .data_RAM3 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM3 = .) ;
        PROVIDE(__start_data_SRAM_OC = .) ;
        *(.ramfunc.$RAM3)
        *(.ramfunc.$SRAM_OC)
                . = ALIGN(4) ;
        PROVIDE(__end_data_RAM3 = .) ;
        PROVIDE(__end_data_SRAM_OC = .) ;
     } > SRAM_OC AT>ROM

    /* DATA section for BOARD_SDRAM */

    .data_RAM4 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM4 = .) ;
        PROVIDE(__start_data_BOARD_SDRAM = .) ;
        *(.ramfunc.$RAM4)
        *(.ramfunc.$BOARD_SDRAM)
                . = ALIGN(4) ;
        PROVIDE(__end_data_RAM4 = .) ;
        PROVIDE(__end_data_BOARD_SDRAM = .) ;
     } > BOARD_SDRAM AT>ROM

    /* DATA section for NCACHE_REGION */

    .data_RAM5 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM5 = .) ;
        PROVIDE(__start_data_NCACHE_REGION = .) ;
        *(.ramfunc.$RAM5)
        *(.ramfunc.$NCACHE_REGION)
                . = ALIGN(4) ;
        PROVIDE(__end_data_RAM5 = .) ;
        PROVIDE(__end_data_NCACHE_REGION = .) ;
     } > NCACHE_REGION AT>ROM

    /* MAIN DATA SECTION */
    .uninit_RESERVED (NOLOAD) : ALIGN(4)
    {
        _start_uninit_RESERVED = .;
        KEEP(*(.bss.$RESERVED*))
       . = ALIGN(4) ;
        _end_uninit_RESERVED = .;
    } > SRAM_DTC AT> SRAM_DTC

    /* Main DATA section (SRAM_DTC) */
    .data : ALIGN(4)
    {
       FILL(0xff)
       _data = . ;
       PROVIDE(__start_data_RAM = .) ;
       PROVIDE(__start_data_SRAM_DTC = .) ;
       *(.ramfunc*)
       KEEP(*(CodeQuickAccess))
       KEEP(*(DataQuickAccess))
       *(RamFunction)
       *(NonCacheable.init)
       *(.data*)
       . = ALIGN(4) ;
       _edata = . ;
       PROVIDE(__end_data_RAM = .) ;
       PROVIDE(__end_data_SRAM_DTC = .) ;
    } > SRAM_DTC AT>ROM

    /* BSS section for SRAM_ITC */
    .bss_RAM2 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM2 = .) ;
       PROVIDE(__start_bss_SRAM_ITC = .) ;
               . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM2 = .) ;
       PROVIDE(__end_bss_SRAM_ITC = .) ;
    } > SRAM_ITC AT> SRAM_ITC

    /* BSS section for SRAM_OC */
    .bss_RAM3 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM3 = .) ;
       PROVIDE(__start_bss_SRAM_OC = .) ;
        *(.bss*)
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM3 = .) ;
       PROVIDE(__end_bss_SRAM_OC = .) ;
    } > SRAM_OC AT> SRAM_OC

    /* BSS section for BOARD_SDRAM */
    .bss_RAM4 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM4 = .) ;
       PROVIDE(__start_bss_BOARD_SDRAM = .) ;
               . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM4 = .) ;
       PROVIDE(__end_bss_BOARD_SDRAM = .) ;
    } > BOARD_SDRAM AT> BOARD_SDRAM

    /* BSS section for NCACHE_REGION */
    .bss_RAM5 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM5 = .) ;
       PROVIDE(__start_bss_NCACHE_REGION = .) ;
               . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM5 = .) ;
       PROVIDE(__end_bss_NCACHE_REGION = .) ;
    } > NCACHE_REGION AT> NCACHE_REGION

    /* MAIN BSS SECTION */
    .bss : ALIGN(4)
    {
        _bss = .;
        PROVIDE(__start_bss_RAM = .) ;
        PROVIDE(__start_bss_SRAM_DTC = .) ;
       *(NonCacheable)
        *(.bss*)
        *(COMMON)
        . = ALIGN(4) ;
        _ebss = .;
        PROVIDE(__end_bss_RAM = .) ;
        PROVIDE(__end_bss_SRAM_DTC = .) ;
        PROVIDE(end = .);
    } > SRAM_DTC AT> SRAM_DTC

    /* NOINIT section for SRAM_ITC */
    .noinit_RAM2 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM2 = .) ;
       PROVIDE(__start_noinit_SRAM_ITC = .) ;
       *(.noinit.$RAM2)
       *(.noinit.$SRAM_ITC)
       *(.noinit.$RAM2.*)
       *(.noinit.$SRAM_ITC.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM2 = .) ;
       PROVIDE(__end_noinit_SRAM_ITC = .) ;
    } > SRAM_ITC AT> SRAM_ITC

    /* NOINIT section for SRAM_OC */
    .noinit_RAM3 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM3 = .) ;
       PROVIDE(__start_noinit_SRAM_OC = .) ;
       *(.noinit.$RAM3)
       *(.noinit.$SRAM_OC)
       *(.noinit.$RAM3.*)
       *(.noinit.$SRAM_OC.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM3 = .) ;
       PROVIDE(__end_noinit_SRAM_OC = .) ;
    } > SRAM_OC AT> SRAM_OC

    /* NOINIT section for BOARD_SDRAM */
    .noinit_RAM4 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM4 = .) ;
       PROVIDE(__start_noinit_BOARD_SDRAM = .) ;
       *(.noinit.$RAM4)
       *(.noinit.$BOARD_SDRAM)
       *(.noinit.$RAM4.*)
       *(.noinit.$BOARD_SDRAM.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM4 = .) ;
       PROVIDE(__end_noinit_BOARD_SDRAM = .) ;
    } > BOARD_SDRAM AT> BOARD_SDRAM

    /* NOINIT section for NCACHE_REGION */
    .noinit_RAM5 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM5 = .) ;
       PROVIDE(__start_noinit_NCACHE_REGION = .) ;
       *(.noinit.$RAM5)
       *(.noinit.$NCACHE_REGION)
       *(.noinit.$RAM5.*)
       *(.noinit.$NCACHE_REGION.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM5 = .) ;
       PROVIDE(__end_noinit_NCACHE_REGION = .) ;
    } > NCACHE_REGION AT> NCACHE_REGION

    /* DEFAULT NOINIT SECTION */
    .noinit (NOLOAD): ALIGN(4)
    {
        _noinit = .;
        PROVIDE(__start_noinit_RAM = .) ;
        PROVIDE(__start_noinit_SRAM_DTC = .) ;
        *(.noinit*)
         . = ALIGN(4) ;
        _end_noinit = .;
       PROVIDE(__end_noinit_RAM = .) ;
       PROVIDE(__end_noinit_SRAM_DTC = .) ;        
    } > SRAM_DTC AT> SRAM_DTC

    /* Reserve and place Heap within memory map */
    .heap :  ALIGN(4)
    {
        _pvHeapStart = .;
        . += _HeapSize;
        . = ALIGN(4);
        _pvHeapLimit = .;
    } > SRAM_DTC

     /* Reserve space in memory for Stack */
    .heap2stackfill  :
    {
        . += _StackSize;
    } > SRAM_DTC
    /* Locate actual Stack in memory map */
    .stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0:  ALIGN(4)
    {
        _vStackBase = .;
        . = ALIGN(4);
        _vStackTop = . + _StackSize;
    } > SRAM_DTC
}

and In Application:

MEMORY
{
  /* Define each memory region */
   /* BOOT_HEADER (r)      : ORIGIN = 0x60000000,  LENGTH = 0x2000       */
   ISR_TABLE (r)        : ORIGIN = 0x60030200,  LENGTH = 0x400       /* Max 256 interrupts on ARM processors */
   FW_VERSION (r)       : ORIGIN = 0x60030600,  LENGTH = 8
   COMMIT_VERSION (r)   : ORIGIN = 0x60030608,  LENGTH = 16

   ROM (rx)             : ORIGIN = 0x60030618,  LENGTH = 0x7CFBE8 /* 8M without space for versions, ISR table and bootloader (192KB) */

   SRAM_DTC (rwx)       : ORIGIN = 0x20000000,  LENGTH = 0x40000 /* 256K bytes (alias RAM) */  
   SRAM_ITC (rwx)       : ORIGIN = 0x0,         LENGTH = 0x40000 /* 256K bytes (alias RAM2) */  
   SRAM_OC (rwx)        : ORIGIN = 0x20200000,  LENGTH = 0xc0000 /* 512K bytes (alias RAM3) */  
   BOARD_SDRAM (rwx)    : ORIGIN = 0x70000000,  LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */  
}

ENTRY(ImageVectorTable)

SECTIONS
{
    /* Image Vector Table and Boot Data for booting from external flash */
    /* .boot_header : ALIGN(4)
    {
        FILL(0xff)
        __boot_hdr_start__ = ABSOLUTE(.) ;
        KEEP(*(.flashconfig))
        . = 0x1000 ;
        KEEP(*(.ivt))
        . = 0x1020 ;
        KEEP(*(.bootdata))
        . = 0x2000;
        __boot_hdr_end__ = ABSOLUTE(.) ;
    } >BOOT_HEADER */

    /* Interrupt vector */
    .isr_vector : ALIGN(8)
    {
        FILL(0xFF)

        KEEP(*(.isr_vector))
    } >ISR_TABLE

    /* Version information */
    .fversion : ALIGN(4)
    {
        FILL(0xff)
        KEEP(*(.fversion))
        KEEP(*(.fversion*))
    } >FW_VERSION

    .cversion : ALIGN(4)
    {
        FILL(0xff)
        KEEP(*(.cversion))
        KEEP(*(.cversion*))
    } >COMMIT_VERSION

    /* Section Table */
    .section_tables : ALIGN(4)
    {
         FILL(0xFF)
        /* Global Section Table */
        . = ALIGN(4) ;
        __section_table_start = .;
        __data_section_table = .;
        LONG(LOADADDR(.data));
        LONG(    ADDR(.data));
        LONG(  SIZEOF(.data));
        LONG(LOADADDR(.data_RAM2));
        LONG(    ADDR(.data_RAM2));
        LONG(  SIZEOF(.data_RAM2));
        LONG(LOADADDR(.data_RAM3));
        LONG(    ADDR(.data_RAM3));
        LONG(  SIZEOF(.data_RAM3));
        __data_section_table_end = .;
        __bss_section_table = .;
        LONG(    ADDR(.bss));
        LONG(  SIZEOF(.bss));
        LONG(    ADDR(.bss_RAM2));
        LONG(  SIZEOF(.bss_RAM2));
        LONG(    ADDR(.bss_RAM3));
        LONG(  SIZEOF(.bss_RAM3));
        __bss_section_table_end = .;
        __section_table_end = . ;
        /* End of Global Section Table */
       . = ALIGN(4);
    } > ROM

    .startup : ALIGN(4)
    {
        KEEP(*(.startup))
	} > ROM


	.text : ALIGN(4)
    {
		KEEP(*(.flashmem*))
		. = ALIGN(4);
		KEEP(*(.init))
		__preinit_array_start = .;
		KEEP(*(.preinit_array))
		__preinit_array_end = .;
		__init_array_start = .;
		KEEP(*(.init_array))
		__init_array_end = .;
		. = ALIGN(4);
        *(.progmem*)
		. = ALIGN(4);
	} > ROM

    /* DATA section for SRAM_ITC */
    .data_RAM2 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM2 = .) ;
        PROVIDE(__start_data_SRAM_ITC = .) ;
        *(.ramfunc.$RAM2)
        *(.ramfunc.$SRAM_ITC)
        *(.fastrun)
		*(.text*)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM2 = .) ;
        PROVIDE(__end_data_SRAM_ITC = .) ;
     } > SRAM_ITC AT>ROM

    .ARM.exidx : {
		__exidx_start = .;
		*(.ARM.exidx* .ARM.extab* .gnu.linkonce.armexidx.*)
		__exidx_end = .;
	} > SRAM_ITC  AT> ROM

    /* DATA section for SRAM_OC */
    .data_RAM3 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM3 = .) ;
        PROVIDE(__start_data_SRAM_OC = .) ;
        *(.ramfunc.$RAM3)
        *(.ramfunc.$SRAM_OC)
                . = ALIGN(4) ;
        PROVIDE(__end_data_RAM3 = .) ;
        PROVIDE(__end_data_SRAM_OC = .) ;
     } > SRAM_OC AT>ROM
     
    /* MAIN DATA SECTION */
    .uninit_RESERVED (NOLOAD) : ALIGN(4)
    {
        _start_uninit_RESERVED = .;
        KEEP(*(.bss.$RESERVED*))
       . = ALIGN(4) ;
        _end_uninit_RESERVED = .;
    } > SRAM_DTC AT> SRAM_DTC

    /* Main DATA section (SRAM_DTC) */
    .data : ALIGN(4)
    {
       FILL(0xff)
       _data = . ;
       PROVIDE(__start_data_RAM = .) ;
       PROVIDE(__start_data_SRAM_DTC = .) ;
       *(.ramfunc*)
       KEEP(*(CodeQuickAccess))
       KEEP(*(DataQuickAccess))
       *(RamFunction)
       *(NonCacheable.init)
       *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
       *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.data*)))
       KEEP(*(.vectorsram))
       . = ALIGN(4) ;       
       _edata = . ;
       PROVIDE(__end_data_RAM = .) ;
       PROVIDE(__end_data_SRAM_DTC = .) ;
    } > SRAM_DTC AT>ROM

    /* BSS section for SRAM_ITC */
    .bss_RAM2 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM2 = .) ;
       PROVIDE(__start_bss_SRAM_ITC = .) ;
               . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM2 = .) ;
       PROVIDE(__end_bss_SRAM_ITC = .) ;
    } > SRAM_ITC AT> SRAM_ITC

    /* BSS section for SRAM_OC */
    .bss_RAM3 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM3 = .) ;
       PROVIDE(__start_bss_SRAM_OC = .) ;
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM3 = .) ;
       PROVIDE(__end_bss_SRAM_OC = .) ;
    } > SRAM_OC AT> SRAM_OC

    /* MAIN BSS SECTION */
    .bss : ALIGN(4)
    {
        _bss = .;
        PROVIDE(__start_bss_RAM = .) ;
        PROVIDE(__start_bss_SRAM_DTC = .) ;
       *(NonCacheable)
        *(.bss*)
		*(COMMON)
		. = ALIGN(32);
		. = . + 32;
        . = ALIGN(4) ;
        _ebss = .;
        PROVIDE(__end_bss_RAM = .) ;
        PROVIDE(__end_bss_SRAM_DTC = .) ;
        PROVIDE(end = .);
    } > SRAM_DTC AT> SRAM_DTC


	.dmabuffer (NOLOAD) : {
		*(.hab_log)
		*(.dmabuffers)
		. = ALIGN(32);
	} > SRAM_OC

	.externalram (NOLOAD) : {
		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.externalram)))
		. = ALIGN(32);
	} > BOARD_SDRAM

	.text.csf : {
		FILL(0xFF)
		. = ALIGN(1024);
		KEEP(*(.csf))
		__text_csf_end = .;
	} > ROM

	_stext = ADDR(.data_RAM2);
	_etext = ADDR(.data_RAM2) + SIZEOF(.ARM.exidx) + SIZEOF(.data_RAM2);
	_stextload = LOADADDR(.data_RAM2);

	_sdata = ADDR(.data);
	_edata = ADDR(.data) + SIZEOF(.data);
	_sdataload = LOADADDR(.data);

	_sbss = ADDR(.bss);
	_ebss = ADDR(.bss) + SIZEOF(.bss);

	_heap_start = ADDR(.dmabuffer) + SIZEOF(.dmabuffer);
	_heap_end = ORIGIN(SRAM_OC) + LENGTH(SRAM_OC);

	_extram_start = ADDR(.externalram);
	_extram_end = ADDR(.externalram) + SIZEOF(.externalram);

	_itcm_block_count = (SIZEOF(.data_RAM2) + SIZEOF(.ARM.exidx) + 0x7FFF) >> 15;
	_flexram_bank_config = 0xAAAAAAAA | ((1 << (_itcm_block_count * 2)) - 1);
	_estack = ORIGIN(SRAM_DTC) + ((16 - _itcm_block_count) << 15);

	_flashimagelen = __text_csf_end - ORIGIN(ROM);
}


And the jump function in Bootloader:

extern void BOOTLDR_jump_to_application(void)
{
    const uint32_t jump_address =  0x60030200UL;

    MISRA_VIOLATION_11_4
    const uint32_t *const address_to_jump_p = (uint32_t *)jump_address;

    // Load the vector table address of the application
    SCB->VTOR = (jump_address & 0xFFFFFFFFU);

    // Set the MSP to the value found in the application vector table
    __set_MSP(address_to_jump_p[0]);

    // Set the PC to the reset vector value of the application via a function call.
    // The program flow will never return to this point.
    ((void (*)(void))address_to_jump_p[1])();
}

I'm not sure that the difference between LinkerScript of Bootloader and Controller's whether it cause this issues or not?

Thank you for reading my post!

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