RAM is MT40A512M16LY-075:E 2GB. I used MX8M_Mini_DDR4_RPA_v11 with ddr_tool_v3.10 for calibration and it passes without issue. I also ran an over-night test and had no problems. In u-boot I'm seeing the following <see below> when training is run. When compared to the evk the training points are different, the evk is using 2400 1D, 400 1D, 100 1D, and 2400 2D. Am I missing something when porting in the ddr4_timing.c from the DDR tool to u-boot imx_v2018.03_4.14.98_2.1.0?
SPL PMIC
pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
#ifndef CONFIG_IMX8M_LPDDR4
/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
#endif
Also calibrated with and without adjusting the PMIC from the ds file
sysparam set pmic_cfg 0x004b
sysparam set pmic_set 0x2f01 #REG_LOCK
sysparam set pmic_set 0x0d0f #BUCK1_VOLT_RUN 0.85v
sysparam set pmic_set 0x100f #BUCK2_VOLT_RUN 0.85v
sysparam set pmic_set 0x1483 #BUCK5_VOLT .975v
sysparam set pmic_set 0x1728 #BUCK8_VOLT 1.2v
sysparam set pmic_set 0x2f01 #REG_LOCK
I did have to add
busfreq {
status = "disabled";
}
to the device tree otherwise, the system would freeze.
U-Boot SPL 2018.03-dirty (Jul 06 2020 - 17:28:51 +0000)
power_bd71837_init
DDRINFO: start DRAM init
DRAM PHY training for 2400MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
Training PASS
DRAM PHY training for 1336MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
Training FAILED
DRAM PHY training for 2400MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
Training PASS
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Trying to boot from USB SDP
Index 0 1
board_usb_init
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
/* P0 2400mts 1D */
.drate = 2400,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
/* P1 1336mts 1D */
.drate = 1336,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
{
/* P0 2400mts 2D */
.drate = 2400,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
},
};
[ 9.091097] Internal error: undefined instruction: 0 [#1] PREEMPT SMP
[ 9.097580] Modules linked in: wlan(+)
[ 9.101348] CPU: 2 PID: 3101 Comm: ip6tables-resto Not tainted 4.14.98-dirty #6
[ 9.108659] Hardware name: DCI i.MX8MM CBX3G board (DT)
[ 9.113886] task: ffff800073761c00 task.stack: ffff000013f10000
[ 9.119815] PC is at update_curr+0x30/0x224
[ 9.124003] LR is at dequeue_task_fair+0x6c/0x1068
[ 9.128794] pc : [<ffff000008114090>] lr : [<ffff000008117234>] pstate: 200001c5
[ 9.136191] sp : ffff000013f13af0
[ 9.139506] x29: ffff000013f13af0 x28: ffff80007ff97870
[ 9.144821] x27: ffff80007ff97800 x26: ffff0000098f4000
[ 9.150135] x25: ffff800073762250 x24: ffff80007ff97800
[ 9.155449] x23: ffff0000098f2018 x22: 0000000000000001
[ 9.160763] x21: ffff80007ff97870 x20: ffff80007ff97800
[ 9.166076] x19: ffff800073761c80 x18: 0000ffffe572a3ba
[ 9.171390] x17: 0000e450eb474188 x16: ffff00000829ec28
[ 9.176703] x15: 0000000000000006 x14: 00000000ffffffff
[ 9.182018] x13: 0000e450eae27680 x12: 0000e450eae27380
[ 9.187332] x11: 0000000000000000 x10: 0000000000000000
[ 9.192646] x9 : 00000000ffffffff x8 : 000000000000003f
[ 9.197960] x7 : 0000000000000000 x6 : 000000003eefbbb3
[ 9.203274] x5 : 000000021b6c8d5c x4 : 0000000000000000
[ 9.208588] x3 : 00000000000001c0 x2 : 0000000000005a9d
[ 9.213902] x1 : ffff800073761c00 x0 : 000000021b71d27b
