About RGMII Receive Signal Timing in i.MX6DQ.

[keitanagashima]

Dear All,

Hello.

Refer to Figure 55. RGMII Receive Signal Timing Diagram with Internal Delay in IMX6DQAEC(Rev.4).

Could you tell me the spec value? (TsetupT, TholdT, TsetupR, TholdR)

Best Regards,

Keita

[Yuri · Accepted solution]

Hello,

  "RGMII is a DDR-type interface. It means that both rising and falling clock edges sample the data,

ideally in the center on each data burst. This is why the RGMII specification defines the clock-data

skew (delay) of 2 ns, which is 1/4 of the 125-MHz signal period.

    There is no guarantee that processors have that 2-ns skew (delay) built in and count on that this

function is usually built into a modern PHY device, and in both directions. E.g., it looks like this skew

is not mentioned in the i.MX6 documentation.

    Conclusion: the Tsetup/Thold values are not provided due to the fact that they are way shorter than

the required 2-ns skew, thus being kind of irrelevant."

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

https://community.freescale.com/message/330002