I am designing a circuit with DDR mode with internal sampling with Quad SPI.
I have two questions.
The following is described in the NOTE of 10.2.12 Output timing in DDR mode of i.MX 7Dual Applications Processor Reference Manual.
Where is TX_DDR_DELAY_EN the Field of the register?
TX_DDR_DELAY_EN should be set to 1 for DDR mode.
The Serial Clock Frequency in Table 6-50 (Quad SPI configuration parameters) can be set up to 76 MHz in DDR mode.
The half cycle of 76MHz is 6.57ns. ((1 / 76MHz) / 2)
On the other hand, the TIS of Table 82 (Quad SPI Input / Read Timing) of the data sheet states that it is min 8.67ns.
Since the half cycle of 76MHz is shorter than 8.67ns, can't it be used at 76MHz?
Is my way of thinking wrong?
1) refer to the chapter 51.13.1 Module Configuration Register (QuadSPIx_MCR) of imx6sx reference manual, you can find bit 29 TX_DDR_DELAY_EN, I think imx7d should be same
2) if Serial Clock Frequency is 76Mhz, then ths SCK=1/76=13.15ns> Tis+Tih, so I think this is ok
I know what you mean, Since it shall send Read command before reading, the QSPI READ clock frequency is set same as WRITE one in practice. The DTR(DDR) READ clock frequency is limited by Setup time (Tis = 8.67nS Min) and Hold time (Tih = 0nS Min). The minimum DTR WRITE SCK Clock Period is Tck = 20nS for i.mx7D, and it is enough for Tis = 8.67nS Min and Tih = 0nS Min.