as another alternative one can consider LVDSCLK1 (CCM_CLK1_N, CCM_CLK1_P balls)
described in sect.18.7.18 Miscellaneous Register 1 (CCM_ANALOG_MISC1n) i.MX6ULL Reference Manual
https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM
But I didn't see any clock divider option on a sec.18.7.18 for 8MHz clock out from 24MHz.