i.MX27 mDDR Issue

[#1]

i.MX27 and i.MX31 Issues When Interfacing Micron's 78nm mDDRs

Micron is discontinuing some "-75" mDDR parts (133MHz) popular on i.MX27 and i.MX31 designs, newer "-6" are being used to replace the EOL devices. However, loss of data issues may be experienced when i.MX mDDR controller is used to interface with newer Micron's mDDR.

On some cases, the bootloader works, memory tests on RedBoot pass. However, Linux hangs when booting.

Here are the DDR Controller configuration changes that may be used to avoid the issue: (This configuration is not proven to work on every design, but has been validated on at least 3 different boards.)

ESDRAMC Configuration Registers

Set ESDCFG0/1 to 0x0079D72F

0xD800_1004 = 0x79D72F 

Drive Strength Control Registers

Use "Normal". i.MX27 Default. 

Enhanced MDDR Delay Line Configuration Debug Register

Set the ESDCDLYx to 0x002C0000

0xD800_1020 = 0x2C0000 
0xD800_1024 = 0x2C0000 
0xD800_1028 = 0x2C0000 
0xD800_102C = 0x2C0000

[GeorgeA]

We have experienced an issue like this too. None of the above changes helped. What did resolve the issue for us is to set the drive strength in the mDDR to full strength, rather than half.

[chrisruehl]

George,

you gave me the right hint fix my problem booting into Linux.

We are using DDR333 from ALLIANCE AS4C64M16MD1 as replacement for the EOL Samsung chip.

Timing:

/* Set DDR timings */

/* samsung 0x006ac73a */

/* AS4C64M16MD1 0x007eeb3f */

/* txp | tWTR | tRP | tMRD | tWR | tRAS  | tRRD | tCAS | Res |tRCD | tRC */

/* 1 1   1      11    10     1     110     10     11     0    011   1111 */

#define AS4C64M16MD1 (ESDCFG_TXP(3)|ESDCFG_TWTR|ESDCFG_TRP(3)|ESDCFG_TMRD(2)|ESDCFG_TWR|ESDCFG_TRAS(6)|ESDCFG_TRRD(2)|ESDCFG_TCAS(3)|ESDCFG_TRCD(3)|ESDCFG_TRC(15))

#define SAMSUNG1G    (ESDCFG_TXP(3)|            ESDCFG_TRP(2)|ESDCFG_TMRD(2)|ESDCFG_TWR|ESDCFG_TRAS(6)|ESDCFG_TRRD(1)|ESDCFG_TCAS(3)|ESDCFG_TRCD(3)|ESDCFG_TRC(10))

Diving strength

   /* MCIMX27 Multimedia Applications Processor Reference Manual, Rev. 0.4

                         Chapter 4.2.8-18 Drive Strength Control Register 3-13

                         Tuning 3 Address lines A15-A0

                         Tuning 5 low 16bit Data SD15-SD0

                         Tuning 6 high 16bit Data SD31-SD16

                         Tuning 7 CS3_B,CS2_B,SDBA1,SDBA0

                         Tuning 8 SDQx,SDCLK,SDCKEx,SDWE_B,CAS_B,RAS_B,MA0,MQN3-MQN0

                */

    /* Register 3 (DSCR3) controls the driving force parameters of the fast I/O signals */

    write32 DSCR(3), 0x00000000

    /* Register 5 (DSCR5) controls the driving force parameters of the fast I/O signals */

    write32 DSCR(5), 0x00000000

    /* Register 6 (DSCR6) controls the driving force parameters of the fast I/O signals */

    write32 DSCR(6), 0x00000000

    /* Register 7 (DSCR7) controls the driving force parameters of the fast I/O signals */

    write32 DSCR(7), 0x00005005

    /* Register 8 (DSCR8) controls the driving force parameters of the fast I/O signals */

    write32 DSCR(8), 0x15555555

Regards

Chris