How to configure iMX95EVK as PCIe Endpoint and test it using PCIe Endpoint Test Framework

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In this blog, we are going to discuss how we can configure iMX95EVK as PCIe Endpoint and test it using a RC which will be iMX8MM.


Hardware Components

iMX95EVK

iMX8MM
PCIe M.2 Key E Bridge
Ethernet connectivity

Software Components

Linux Factory 6.12.20 BSP

linux-imx source code - https://github.com/nxp-imx/linux-imx/tree/lf-6.12.20-2.0.0


System setup

1.jpg

Step -1 Flash the 6.12.20 BSP on the iMX95 EVK eMMC/SD card and boot with it.

Step-2 Fetch linux-imx 6.12.20 source code from the github repo

GitHub - nxp-imx/linux-imx at lf-6.12.20-2.0.0

Step-3 Make the following changes to arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso as per the following diff:-

 

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso

index a8e3bbc53894..d082688fc1c2 100644

--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso

+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-pcie1-ep.dtso

@@ -11,12 +11,12 @@ &smmu {

 };

-&pcie1 {

+&pcie0 {

        status = "disabled";

 };

-&pcie1_ep {

+&pcie0_ep {

        pinctrl-names = "default";

-       pinctrl-0 = <&pinctrl_pcie1>;

+       pinctrl-0 = <&pinctrl_pcie0>;

        status = "okay";

 };

As you can see, we are trying to enable 'End-point' mode on iMX95EVK's M.2 PCIe 0. The default dtb enables it for PCIe 1. Building the kernel will build this dtb from the dtso changes.


Step-4 SCP the dtb to the board and rename it to "imx95-19x19-evk-pcie0-ep.dtb" to avoid confusion. Copy it to the location - /run/media/boot-mmcblk0p1/

Step-5 Boot the board with this DTB by changing the 'fdtfile' variable at Uboot.

when the kernel boots up with this dtb, you will see the following pcie dmesg logs on the console through which you can verify if the changes have worked:-

root@imx95evk:~# dmesg | grep pcie-ep

[    3.142123] imx6q-pcie 4c300000.pcie-ep: iATU: unroll T, 8 ob, 8 ib, align 4K, limit 1024G

[    3.151767] imx6q-pcie 4c300000.pcie-ep: eDMA: unroll T, 4 wr, 4 rd

root@imx95evk:~#

0x4c300000 is the address of pcie0 controller

Step-6 Execute this script on iMX95EVK - 'conf_pcie0_ep'

2.png

Step-7 Boot iMX8MM board with this dtb - imx8mm-evk.dtb

Step-8 Executing 'lspci' on the iMX8MM, you will see the following output:-

3.png

That's the iMX95EVK Endpoint that you see on the lspci output of iMX8MM RC.

The address space translation window is configured with the help of the info mentioned in 

arch/arm64/boot/dts/freescale/imx8mm.dtsi

gaurav_sharma_0-1762327307740.png

If the readers want to make sense out of the translation window info mentioned in form of 'ranges' property of PCIe node, they can go through this article in which there is a detailed explanation of what is going behind the scenes - Demystifying the PCIe and CPU address space translation in Linux - NXP Community