Overview
The purpose of this document is to provide guidance for FlexIO 8080 display capability. Generally, the 8080 bus interface consists of one chip-select line (CS), one writing-latch line (WR), one reading-latch line (RD), one data/command-select line (RS, also called D/C), and 8 or 16 bidirectional data lines (Data Bus).
Since The FlexIO instance of i.MX 943 support only 16 pins, the demo can only support 8 bit 8080 mode(two pin should be used as WR and RD signal.
Below are pins used in the 8 bit 8080 display.
Panel Setup
The panel in the example is X-LCD-PAR-S035. To use 8 bit 8080 mode, need ser IM[2:0] to be 011.
Connection and Software
i.MX 943
Need pull down SPI8_SEL1 and SPI8_SEL3 of PCA6416 in SW to select Arduino for 8080 pins D[7:4].
Here is the patch for system manager. For quick verification, use flash_m70 when building bootloader.
diff --git a/configs/mx94evk.cfg b/configs/mx94evk.cfg
index 9d46976..90bf089 100755
--- a/configs/mx94evk.cfg
+++ b/configs/mx94evk.cfg
@@ -499,6 +499,9 @@ ENC_PLL OWNER
ENDAT2_1 OWNER
ENDAT2_2 OWNER
ENDAT3_1 OWNER
+GPIO2 OWNER
+GPIO3 OWNER
+FLEXIO1 OWNER
FLEXIO3 OWNER
FLEXIO4 OWNER
FLEXPWM1 OWNER
@@ -515,6 +518,7 @@ HIPERFACE_SAFE1_2 OWNER
HIPERFACE_SAFE2_1 OWNER
HIPERFACE_SAFE2_2 OWNER
IRQSTEER_M7_0 OWNER
+LPI2C6 OWNER
LPIT1 OWNER
LPTMR1 OWNER
LPTMR2 OWNER
@@ -557,6 +561,25 @@ XBAR_DSC3 OWNER
PIN_GPIO_IO24 OWNER
PIN_GPIO_IO25 OWNER
+# 8080
+PIN_GPIO_IO00 OWNER
+PIN_GPIO_IO01 OWNER
+PIN_GPIO_IO02 OWNER
+PIN_GPIO_IO03 OWNER
+PIN_GPIO_IO08 OWNER
+PIN_GPIO_IO09 OWNER
+PIN_GPIO_IO10 OWNER
+PIN_GPIO_IO11 OWNER
+PIN_GPIO_IO12 OWNER
+PIN_GPIO_IO13 OWNER
+PIN_GPIO_IO14 OWNER
+PIN_GPIO_IO15 OWNER
+PIN_GPIO_IO38 OWNER
+
+# I2C6
+PIN_GPIO_IO28 OWNER
Attached imx943_flexio_8080_8bit.zip is patch for m70 demo based on SDK_25_06_00_MCIMX943-EVK.
i.MX 93
Need pull up EXP_SEL(pin4 R4) of ADP5585 in SW to route some pins.
Attached imx93_flexio_8080_8bit.zip is patch for m33 demo based on SDK_25_06_00_MCIMX93-EVK. The running status is similar as i.MX943.
