kw 45 spi frequency

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kw 45 spi frequency

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trent
Contributor II

hi,

i am currently testing spi communication between the KW45B41Z-EVK and the NCJ29D6. The NCJ29D6 EVK has successfully communicated with the S32K144 EVK via SPI.

The SPI frequency for the NCJ29D6 is set to 10 MHz. I have also modified the SPI frequency for the KW45 to 10 MHz. However, I am unable to achieve this. In the code snippet below, the SPI frequency reached 10 MHz a few times, but then it has not been able to reach 10 MHz again.

The KW45 is the NXP KW45EVK.

HI,

我现在测试 KW45B41Z-EVK 与 NCJ29D6 进行SPI 通信。NCJ29D6 EVK与 S32K144 EVK SPI 通讯成功过,

NCJ29D6 的 SPI频率为 10MHZ。所有我将 KW45 SPI频率 也修改为10MHZ。但是我无法做到。下图是部分KW45的代码有过几次 SPI频率达到10MHZ,之后就再也无法得到 10MHZ ?。

KW45为 NXP 的KW45EVK。

trent_0-1725595212651.png

 

trent_1-1725595225952.png

trent_2-1725595251694.pngtrent_3-1725595279449.png

 

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Alexandre_Moulinet
NXP Employee
NXP Employee

Hi @Aladdine,

You are stuck at 6MHz because you have not considered all the clock dividers.

Starting with the lpspi_interrupt_b2b_master example from the SDK, below are the things to take into consideration:

- The clock for peripherals is generated by the MRCC block from the FIRC (Fast Internal Reference Clock):

Alexandre_Moulinet_2-1733940855765.png

The FIRC range is configured via the below configuration and APIs:

[clock_config.c file]

Alexandre_Moulinet_3-1733941098881.png

And the above configuration set the FIRC clock to 96MHz and is applied in the void BOARD_BootClockRUN(void) API:

Alexandre_Moulinet_4-1733941340675.png

 

- Each peripheral have a dedicated MRCC register to configure the source clock of the MRCC of this peripheral and a divider to scale the output clock:

Alexandre_Moulinet_1-1733940646938.png

This action is performed in the main() function here:

Alexandre_Moulinet_5-1733941727925.png

As you can see, by default, the source frequency of the LPSPI0 is equal to 6MHz, which represents the limitation you are seeing.

Therefore, when calling LPSPI_MasterInit() API, the baudrate calculation is based on this frequency value, which is lower than 10MHz!

 

To get to 9.6MHz, the easiest solution is to change the divider from 16 to a value compromised between 1 and 9.
I personally tested with a divider set to 1 (kSCG_SysClkDivBy1) and I managed to get a source clock for the LPSPI0 to 9.6MHz:

Alexandre_Moulinet_6-1733941995109.png

Please try this and let us know if you can get the LPSPI0 clock to 9.6MHz.

 

Regards,
Alex

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Alexandre_Moulinet
NXP Employee
NXP Employee

Hi @Aladdine,

You are stuck at 6MHz because you have not considered all the clock dividers.

Starting with the lpspi_interrupt_b2b_master example from the SDK, below are the things to take into consideration:

- The clock for peripherals is generated by the MRCC block from the FIRC (Fast Internal Reference Clock):

Alexandre_Moulinet_2-1733940855765.png

The FIRC range is configured via the below configuration and APIs:

[clock_config.c file]

Alexandre_Moulinet_3-1733941098881.png

And the above configuration set the FIRC clock to 96MHz and is applied in the void BOARD_BootClockRUN(void) API:

Alexandre_Moulinet_4-1733941340675.png

 

- Each peripheral have a dedicated MRCC register to configure the source clock of the MRCC of this peripheral and a divider to scale the output clock:

Alexandre_Moulinet_1-1733940646938.png

This action is performed in the main() function here:

Alexandre_Moulinet_5-1733941727925.png

As you can see, by default, the source frequency of the LPSPI0 is equal to 6MHz, which represents the limitation you are seeing.

Therefore, when calling LPSPI_MasterInit() API, the baudrate calculation is based on this frequency value, which is lower than 10MHz!

 

To get to 9.6MHz, the easiest solution is to change the divider from 16 to a value compromised between 1 and 9.
I personally tested with a divider set to 1 (kSCG_SysClkDivBy1) and I managed to get a source clock for the LPSPI0 to 9.6MHz:

Alexandre_Moulinet_6-1733941995109.png

Please try this and let us know if you can get the LPSPI0 clock to 9.6MHz.

 

Regards,
Alex

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Aladdine
Contributor II

Hello @Alexandre_Moulinet,

 

You've pinpointed the exact issue, it seems that we've intialized LPSPI1 two times, once in the clock_config.c file and the second one at the beginning of the main file, right after calling the BOARD_ClockRUN method. 

After removing this line, we've successfully reached 9.6MHz as you described.

Thank you for the correction! That was a silly question on my part, but I appreciate your patience and help.

Best regards,

 

Aladdine.

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Aladdine
Contributor II

Hello @Ricardo_Zamora

Could you provide us the solution that you gave to @trent because we are encountering the same issue being that we're stuck to 6MHz approx. for the LPSPI0/1. 

We've correctly configured the clock tree with the maximum speed we could set and the LPSPI0/1 to 48MHz through each block, using the FIRC source which is running at 192MHz and defined a baudrate to 10MHz as we're trying to achieve it. 

The used example is the lpspi_interrupt_b2b_master provided for the same version that you have (v2.16.000), please see the attachment below for our exact configuration.

Any assistance would be appreciated.

Best regards, 

Aladdine.

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Ricardo_Zamora
NXP TechSupport
NXP TechSupport

Hello,

 

Hope you are doing well. Are you using any SDK example as a base? What SDK version are you using? Have you tried with some example just modifying the baudrate?

 

Best Regards,

Ricardo

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trent
Contributor II

Hello,

thank you for your reply.

the sdk are using is sdk_2_12_5_KW45B41Z83xxxA, and the version is 2.12.5. I have tried both  lpspi_interrupt_b2b_transfer_master  and  lpspi_polling_b2b_transfer_master

I have set the maximum SPI baud rate to 1 MHz, and any higher rate causes issues. How can I modify the SPI baud rate to 10 MHz?

 

使用的SDK是 SDK_2_12_5_KW45B41Z83xxxA Version 为 2.12.5 ,我试过lpspi _interrupt_b2b_transfer_master h和 lpspi_polling_b2b_transfer_master,这个两个例程。

我试过SPI的波特率最大修改到1MHZ。波特率再大就有问题了。我要如何才能将 SPI的波特率修改到 10MHZ?

 

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Ricardo_Zamora
NXP TechSupport
NXP TechSupport

Hello,

 

If you modify the TRANSFER_BAUDRATE and the divValue of theCLOCK_SetIpSrcDiv in the kw45b41zevk_lpspi_interrupt_b2b_master, you could get a baudrate around 9.6MHz.

 

This is working on my side. I am using SDK v2.16.000

 

Regards,

Ricardo

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trent
Contributor II

Hello,

I want to use spi in polling mode. i tested lpspi_polling_transfer_master and made some modifications to it. However, the SCK signal is sometimes not continuous, as shown in the image. Is there any way to improve this?

我想要以轮询方式使用 SPI ,我测试了 lpspi_polling_transfer_master,对它进行了如下修改。但是SCK有时不连续,如下图所显,有什么办法可以改进吗?

 

 
 
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Ricardo_Zamora
NXP TechSupport
NXP TechSupport

Hello,

 

With the same modifications to the "kw45b41zevk_lpspi_polling_b2b_transfer_master" example, you can get the same frequency.

 

Looks like the behavior you are seeing is related to the logic analyzer. Is the communication not working?

 

Regards,

Ricardo

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trent
Contributor II

yes, referring to the "NCJ29D6 -KW45 TESTWAREHOST USER GUIDE," we are testing the SPI communication between NCJ29D6 and KW45. The communication is not working; KW45 resets NCJ29D6, and the KW45 EVK does not receive the startup sequence from NCJ29D6. KW45 is an NXP EVK, while NCJ29D6 is a custom board we made that can communicate via SPI with the S32K144. I hope you can provide me with some suggestions.

是的,参考 《NCJ29D6 -KW45 TESTWAREHOST USER GUIDE》,测试 NCJ29D6 与 KW45 的 SPI 通讯。 KW45复位 NCJ29D6 ,KW45EVK 收不到 NCJ29D6的启动 sequence,KW45是 NXP的EVK。NCJ29D6是我们自己制作的板子,它可以S32K144通过SPI通讯。希望您能给我一些建议。 
 
 
 
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Ricardo_Zamora
NXP TechSupport
NXP TechSupport

Hello,

 

I sent you a private message!

 

Regards,

Ricardo

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