Good day Gerado Rodriguez.
Please clarify the situation with SPIFI hardware interface in QN9080 chip.
I have create the simple low leve driver that support serial Flash memory from Microchip SST26VF064B.
Lets's speak about the simple command 0x05 (Read JEDEC ID). This command use only opcode (0x05) and
after that, reads 3-bytes info (Manufacturer ID, Memory type, Chip ID) back.
SPIFI interface configured for use only four pins (kSPIFI_DualMode): SCK, CS, MISO, MOSI at:
MOSI: {pin_num: '21', peripheral: SPIFI0, signal: 'IO, 0', pin_signal: GPIOA24/ACMP0N/CS6/ETM_TRACEDAT0/CTIMER3_CAP0/RFE_RX_EN/FC3_SSEL1/SPIFI_IO0, pull_control: Pull_up, drive_strength: high}
MISO: {pin_num: '20', peripheral: SPIFI0, signal: 'IO, 1', pin_signal: GPIOA25/ACMP0P/CS7/ETM_TRACEDAT1/CTIMER3_CAP1/RFE_TX_EN/FC3_SSEL0/SPIFI_IO1, pull_control: Pull_up, drive_strength: high}
SCK: {pin_num: '25', peripheral: SPIFI0, signal: SCK, pin_signal: GPIOA20/QDEC1_A/SCT0_OUT1/CTIMER2_MAT0/SWO/FC1_RTS_SCL/SPIFI_CLK, pull_control: Pull_up, drive_strength: high}
CS: {pin_num: '17', peripheral: SPIFI0, signal: CSN, pin_signal: GPIOA28/CLK_AHB/ETM_TRACECLK/RTC_CAP/FC1_SCK/SD_DAC/SPIFI_CSN, pull_control: Pull_up, drive_strength: high}
The function that configures SPIFI as SPI in MODE0
/*-----------------------------------------------------------------------------------*/
int ext_flash_init()
{
// SPIFI configuration structure
spifi_config_t config = {0};
// Get default SPIFI configuration
SPIFI_GetDefaultConfig(&config);
// SPIFI uses only IO1:0 (MISO/MOSI)
config.dualMode = kSPIFI_DualMode;
// Disable prefetch
//config.disablePrefetch = true;
// Disable feedback clock
//config.isFeedbackClock = false;
// Initialize SPIFI
SPIFI_Init(SPIFI_PERIPHERAL, &config);
return 0;
}
The function that reads JEDEC ID:
/*-----------------------------------------------------------------------------------*/
/** Read JEDEC ID from external SPI memory
* JEDEC ID consists from 3 bytes:
* 1 - Manufacturer ID
* 2 - SPI Memory type
* 3 - CHIP ID
* \param[in] id Pointer to the 3-byte array where JEDEC ID stored
* \return '0' - for success operation, '-1' - error detected
*/
int ext_flash_Read_ID(unsigned char id[3])
{
unsigned int value;
// {dataLen, isPollMode, direction, intermediateBytes, format, type, opcode}
spifi_command_t read_jedec_id={4 , false, kSPIFI_DataInput, 0, kSPIFI_CommandAllSerial, kSPIFI_CommandOpcodeOnly, 0x9F};
// Check supplied pointer to the JEDEC ID 3-bytes answer
if (id == 0) {
return (-1);
}
// Reset the SPIFI for switch to the command mode
//SPIFI_ResetCommand(SPIFI_PERIPHERAL);
// Send JEDEC_ID command
SPIFI_SetCommand(SPIFI_PERIPHERAL, &read_jedec_id);
// Read 3-bytes answer from Flash
value = SPIFI_ReadData(SPIFI_PERIPHERAL);
// Reload Manufacturer ID
id[0] = (unsigned char) value;
// Reload Flash device Type
id[1] = (unsigned char) (value >> 8);
// Reload Flash device ID
id[2] = (unsigned char) (value >> 16);
return (0);
}
If I specify in the 'spifi_command_t' structure 'dataLen' field equal to 4 the function successfuly read JEDEC ID: 0xBF, 0x26, 0x43.
If I specify in the 'spifi_command_t' structure 'dataLen' field equal to 3 (as mentioned in SST26VF064B datasheet) after call SPIFI_ReadData function 'HardFault_Handler' is executed. But data is read from Flash memory as you can see at the attached picture (3-bytes answer during JEDEC ID Read).
As specified in the MCUXpresso SDK API Reference Manual_QN908x.pdf at page 392 in the description of the 'SPIFI_ReadData' function:
"Users should notice before call this function, the data length field in command register shall larger than 4, otherwise a hardfault will happen."
So the manual of the QN9080 chip is not correctly describe the "CMD - SPIFI command register".
As I understand DATALEN (13:0) must be multiple to 4 in order to avoid hardfault.
Please clarify this situation (how to avoid hardfault during SPIFI read not multiple to 4).
In the attachment, you can find diagrams of the SPIFI communication for reading JEDEC ID.
Read 4-bytes answer during JEDEC ID Read:

Read 3-bytes answer during JEDEC ID Read:
