KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep)

[hyama]

Hello,

I am reading the KW47 Reference Manual and I am confused about the relationship between the WDOG low-power modes and the system power modes.

In the WDOG chapter, the Control and Status register contains the following bits:

- WAIT:
"Enables WDOG to operate when the chip is in Wait mode."

- STOP:
"Enables WDOG to operate when the chip is in Stop mode."

The WDOG chapter also states that:

- The selected WDOG clock source must remain active in Stop mode.
- For Debug and Stop modes, a clock source other than the bus clock must be used.

On the other hand, the Power Modes chapter describes:

Sleep mode:
- CPU execution halted
- Core clock gated off
- System clock and bus clock may continue running

Deep Sleep mode:
- Core clock gated off
- System clock gated off
- Bus clock gated off

Based on these descriptions, it seems reasonable to interpret:

- Wait mode ≈ Sleep mode
- Stop mode ≈ Deep Sleep mode

However, I have not been able to find any explicit statement in the Reference Manual confirming this mapping.

My questions are:

1. Does WDOG Wait mode correspond to the Power Mode Sleep mode on KW47?
2. Does WDOG Stop mode correspond to the Power Mode Deep Sleep mode on KW47?
3. Or are Wait/Stop WDOG-specific CPU states that are different from the SoC power modes?
4. Is there any Reference Manual section or Application Note that explicitly describes this relationship?

Thank you for your help.

[sofiaurueta]

Hello, hope you are doing well.

The terminology used in the KW47 Reference Manual is consistent with interpreting the WAIT and STOP fields in the WDOG control register as references to chip/core low-power states, rather than as WDOG-specific CPU states. I would describe the relationship as functional correspondence rather than a strict equivalence.

In that sense, WDOG WAIT corresponds to the Wait/Sleep class condition, where CPU execution is halted but the system and bus clocks may remain available. WDOG STOP corresponds to the Stop/Deep-Sleep class condition, where the core, system, and bus clocks are gated and the watchdog can continue only if it is configured to use a clock source that remains active in that mode.

Best regards,
Sofia.

[hyama]

@sofiaurueta 

I performed some additional testing and updated the post with my findings above.
Could you please let me know if my interpretation is correct?

Thank you.

[sofiaurueta]

Hi @hyama , I apologize for the late reply.

Are you testing with any example from the SDK? How are you confirming that the device is entering Deep Sleep mode?

From the behavior you described, it is possible that the device is only entering Sleep mode. If the device were entering Deep Sleep, the results would be the opposite: STOP=1 (Case 3) should have caused the timeout, and WAIT=1 (Case 2) should have had no effect. The fact that it is WAIT=1 that triggers the reset is consistent with the device entering Sleep mode, not Deep Sleep.

Answering your questions:

1. When the device enters a low-power mode through PWR_EnterLowPower(), is WDOG operation controlled by the WAIT bit or the STOP bit?

CS[WAIT] and CS[STOP] are independent controls for independent modes where CS[WAIT] controls WDOG operation in Sleep mode, and CS[STOP] controls WDOG operation in Deep Sleep mode.
In the case that the device enters Sleep mode, CS[WAIT] is the active control. CS[STOP] has no effect here because Deep Sleep is not entered. If the device were instead configured to enter Deep Sleep, CS[STOP] would be the active control.

2. Does the observed result indicate that the device is actually entering Sleep mode rather than Deep Sleep mode, or should it be interpreted as entering Deep Sleep mode?

The results are consistent with Sleep mode entry and are inconsistent with Deep Sleep. Based on the three test cases, Sleep mode is being entered.

3. Does the STOP bit correspond to the Deep Sleep mode described in the Power Modes chapter, or does it refer to a different low-power state?

Based on the documentation, CS[STOP] corresponds to Deep Sleep, and the behavior observed in the tests is consistent with this (assuming that Deep Sleep was not entered).

4. How should the following entries in Table 225 be interpreted with respect to the WDOG WAIT and STOP control bits?

The "Optional" for Deep Sleep means the WDOG can operate in Deep Sleep if CS[STOP]=1 and a clock source other than the bus clock is configured. For Debug and Stop modes, a clock source other than the bus clock must be used. Using the bus clock the watchdog can be "enabled" architecturally but its clock is gone, unless a different clock source is selected, for example, 32K_CLK.

Best regards,
Sofia.

[hyama]

Hi @sofiaurueta 
Thank you for your previous explanation.

>Are you testing with any example from the SDK? How are you confirming that the device is entering Deep Sleep mode?

Regarding your question, the test was not performed on an SDK example project. It was performed on our application based on the NXP SDK.
To verify whether the device enters Deep Sleep mode, I performed some additional investigation and found that the following path is executed when entering low-power mode:

vPortSuppressTicksAndSleep()
-> PWR_EnterLowPower()
-> PM_EnterLowPower()
-> PM_EnterLowPowerMode()
-> CMC_EnterLowPowerMode()

In CMC_EnterLowPowerMode(), the SDK sets the SLEEPDEEP bit in the SCB->SCR register before executing WFI.
Our understanding is that setting the SLEEPDEEP bit and executing WFI means that the device enters Deep Sleep mode. Could you please confirm whether this understanding is correct for KW47?
I am asking because my WDOG test results appear to depend on the WAIT bit rather than the STOP bit.

Thank you for your help.

[hyama]

Hello Sofia,

Thank you for your previous explanation.

Based on your reply, my understanding is:

- WDOG WAIT corresponds to a Wait/Sleep-class low-power condition.
- WDOG STOP corresponds to a Stop/Deep-Sleep-class low-power condition.
- The relationship is a functional correspondence rather than a strict one-to-one mapping.

After reviewing the KW47 Reference Manual again, I found the following section:

28.4 Module operation in low power modes
Table 225: Cortex M33 core module operation in low power modes

For WDOGx, the table shows:

- Sleep : ON
- Deep Sleep : Optional
- Power Down : Optional
- Deep Power Down : OFF

From this table, I interpreted that WDOG operation can be configured in at least Deep Sleep and Power Down modes.

To better understand the behavior, I performed a test using a KW47-Loc evaluation board.

Test conditions:

- WDOG enabled
- WDOG refresh is performed from vApplicationIdleHook()
- PWR_EnterLowPower() is executed from FreeRTOS vPortSuppressTicksAndSleep()
- Observe whether a watchdog reset occurs after entering the low-power state

Test results:

Case 1
WAIT=0, STOP=0
→ No watchdog reset occurred

Case 2
WAIT=1, STOP=0
→ Watchdog reset occurred

Case 3
WAIT=0, STOP=1
→ No watchdog reset occurred

My interpretation is that when a watchdog reset occurred, the device entered a low-power state where vApplicationIdleHook() was no longer executed while the watchdog continued running and eventually timed out.

However, a watchdog reset occurred only when WAIT=1 and STOP=0, while no watchdog reset occurred when STOP=1.

Because of this result, I am having difficulty understanding how the WAIT and STOP bits are actually applied to watchdog operation during low-power modes.

Could you please clarify the following points?

1. When the device enters a low-power mode through PWR_EnterLowPower(), is WDOG operation controlled by the WAIT bit or the STOP bit?

2. Does the observed result indicate that the device is actually entering Sleep mode rather than Deep Sleep mode, or should it be interpreted as entering Deep Sleep mode?

3. Does the STOP bit correspond to the Deep Sleep mode described in the Power Modes chapter, or does it refer to a different low-power state?

4. How should the following entries in Table 225 be interpreted with respect to the WDOG WAIT and STOP control bits?
- WDOGx : Optional (Deep Sleep)
- WDOGx : Optional (Power Down)

Thank you for your support.