KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep)

[hyama]

Hello,

I am reading the KW47 Reference Manual and I am confused about the relationship between the WDOG low-power modes and the system power modes.

In the WDOG chapter, the Control and Status register contains the following bits:

- WAIT:
"Enables WDOG to operate when the chip is in Wait mode."

- STOP:
"Enables WDOG to operate when the chip is in Stop mode."

The WDOG chapter also states that:

- The selected WDOG clock source must remain active in Stop mode.
- For Debug and Stop modes, a clock source other than the bus clock must be used.

On the other hand, the Power Modes chapter describes:

Sleep mode:
- CPU execution halted
- Core clock gated off
- System clock and bus clock may continue running

Deep Sleep mode:
- Core clock gated off
- System clock gated off
- Bus clock gated off

Based on these descriptions, it seems reasonable to interpret:

- Wait mode ≈ Sleep mode
- Stop mode ≈ Deep Sleep mode

However, I have not been able to find any explicit statement in the Reference Manual confirming this mapping.

My questions are:

1. Does WDOG Wait mode correspond to the Power Mode Sleep mode on KW47?
2. Does WDOG Stop mode correspond to the Power Mode Deep Sleep mode on KW47?
3. Or are Wait/Stop WDOG-specific CPU states that are different from the SoC power modes?
4. Is there any Reference Manual section or Application Note that explicitly describes this relationship?

Thank you for your help.

[sofiaurueta]

Hello, hope you are doing well.

The terminology used in the KW47 Reference Manual is consistent with interpreting the WAIT and STOP fields in the WDOG control register as references to chip/core low-power states, rather than as WDOG-specific CPU states. I would describe the relationship as functional correspondence rather than a strict equivalence.

In that sense, WDOG WAIT corresponds to the Wait/Sleep class condition, where CPU execution is halted but the system and bus clocks may remain available. WDOG STOP corresponds to the Stop/Deep-Sleep class condition, where the core, system, and bus clocks are gated and the watchdog can continue only if it is configured to use a clock source that remains active in that mode.

Best regards,
Sofia.

[hyama]

Hello Sofia,

Thank you for your previous explanation.

Based on your reply, my understanding is:

- WDOG WAIT corresponds to a Wait/Sleep-class low-power condition.
- WDOG STOP corresponds to a Stop/Deep-Sleep-class low-power condition.
- The relationship is a functional correspondence rather than a strict one-to-one mapping.

After reviewing the KW47 Reference Manual again, I found the following section:

28.4 Module operation in low power modes
Table 225: Cortex M33 core module operation in low power modes

For WDOGx, the table shows:

- Sleep : ON
- Deep Sleep : Optional
- Power Down : Optional
- Deep Power Down : OFF

From this table, I interpreted that WDOG operation can be configured in at least Deep Sleep and Power Down modes.

To better understand the behavior, I performed a test using a KW47-Loc evaluation board.

Test conditions:

- WDOG enabled
- WDOG refresh is performed from vApplicationIdleHook()
- PWR_EnterLowPower() is executed from FreeRTOS vPortSuppressTicksAndSleep()
- Observe whether a watchdog reset occurs after entering the low-power state

Test results:

Case 1
WAIT=0, STOP=0
→ No watchdog reset occurred

Case 2
WAIT=1, STOP=0
→ Watchdog reset occurred

Case 3
WAIT=0, STOP=1
→ No watchdog reset occurred

My interpretation is that when a watchdog reset occurred, the device entered a low-power state where vApplicationIdleHook() was no longer executed while the watchdog continued running and eventually timed out.

However, a watchdog reset occurred only when WAIT=1 and STOP=0, while no watchdog reset occurred when STOP=1.

Because of this result, I am having difficulty understanding how the WAIT and STOP bits are actually applied to watchdog operation during low-power modes.

Could you please clarify the following points?

1. When the device enters a low-power mode through PWR_EnterLowPower(), is WDOG operation controlled by the WAIT bit or the STOP bit?

2. Does the observed result indicate that the device is actually entering Sleep mode rather than Deep Sleep mode, or should it be interpreted as entering Deep Sleep mode?

3. Does the STOP bit correspond to the Deep Sleep mode described in the Power Modes chapter, or does it refer to a different low-power state?

4. How should the following entries in Table 225 be interpreted with respect to the WDOG WAIT and STOP control bits?
- WDOGx : Optional (Deep Sleep)
- WDOGx : Optional (Power Down)

Thank you for your support.