Working with RW612's USART I stumble into the following problem:
I'm enabling the USART RXTIMEOUT interrupt using the SDK-provided API:
USART_EnableInterrupts(USART3, kUSART_RxTimeoutInterruptEnable);
and I'm also setting the interrupt using the provided API to configure it:
USART_CalcTimeoutConfig(timeMicroSec,
&rxTimeoutCfg.prescaler,
&rxTimeoutCfg.counter,
CLOCK_GetFlexCommClkFreq(flexCommId));
rxTimeoutCfg.enable = true;
rxTimeoutCfg.resetCounterOnEmpty = false;
rxTimeoutCfg.resetCounterOnReceive = true;
// Disable UART in order to configure timeout
mp_uartBase->CFG &= ~USART_CFG_ENABLE_MASK;
USART_SetRxTimeoutConfig(mp_uartBase, &rxTimeoutCfg);
USART_EnableInterrupts(mp_uartBase, kUSART_RxTimeoutInterruptEnable);
// Re-enable timeout
mp_uartBase->CFG |= USART_CFG_ENABLE_MASK;
The interrupt is triggering as expected, however I'm unable to clear the interrupt.
According to RM00278 28.1.12:

However, from the fsl_usart.c driver (SDK 24.12) we have:
/* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
As the fsl driver wouldn't even attempt to clear write the FIFOSTAT->RXTIMEOUT timeout bit I tried to write to it directly:
// Clear the timeout interrupt
mp_uartBase->FIFOSTAT |= USART_FIFOSTAT_RXTIMEOUT_MASK;
Unfortunately, this doesn't work and the interrupt is never cleared.
Could you please advise on how RXTIMEOUT interrupt is cleared?